在verilog上实现了带有时钟分频和不同输出的测试台

Question

对于以下代码，这是一个7段59秒计数器，我试图实现一个测试台。我有两个问题:一个是我使用术语q[24]作为内部时钟，使其计数近似秒，但在测试台中，我应该能够看到不同的输出，而无需实现数千个波塞奇时钟。另一个麻烦是，我想在测试台中看到寄存器[3:0]unidad和[3:0]decena的输出，它们是7段面板上的每个数字，但在代码中，这些不像在或输出中使用，而是作为一个内部变量。

我怎样才能实现这样一个模拟，在合理的时间内显示decena/unidad输出?谢谢。

module cont(
   input clock,
   input reset,
   output reg [6:0]segm,
   output [3:0]an
   );
reg [3:0]unidad; 
reg [3:0]decena; 
reg [24:0] q;
always @(posedge clock or posedge reset)
    begin
        if(reset == 1)
         q <= 0;
        else
            q <= q + 1;
    end
always @ (posedge q[24] or posedge reset)
 begin
  if (reset) begin
   unidad <= 0;
   decena <= 0;
  end
  else if (unidad==4'd9) 
    begin  
    unidad <= 0;
     if (decena==4'd5) 
      decena <= 0;
        else
         decena <= decena + 1;
     end
   else
    unidad <= unidad + 1;
  end
reg [6:0]sseg;
reg [3:0]an_temp;
always @ (*)
 begin
  case(q[13])
   1'b0 : 
    begin
     sseg = unidad;
     an_temp = 4'b1110;
    end
   1'b1 :
    begin
     sseg = decena;
     an_temp = 4'b1101;
    end
  endcase
 end
assign an = an_temp;
always @ (*)
 begin
  case(sseg)
   4'd0 : segm = 7'b1000000; //0
   4'd1 : segm = 7'b1111001; //1
   4'd2 : segm = 7'b0100100; //2
   4'd3 : segm = 7'b0110000; //3
   4'd4 : segm = 7'b0011001; //4
   4'd5 : segm = 7'b0010010; //5
   4'd6 : segm = 7'b0000010; //6
   4'd7 : segm = 7'b1111000; //7
   4'd8 : segm = 7'b0000000; //8
   4'd9 : segm = 7'b0010000; //9
   default : segm = 7'b1111111; 
  endcase
 end
endmodule

Answer 1

可以使计数器更接近测试台中感兴趣的值。您可以通过两种样式来实现。

1)强制计数器接近您感兴趣的值，并生成一些时钟周期。

2)强制你感兴趣的位，等待一些时钟周期。

在这种情况下，'h1000和'h1000000是感兴趣的值或第24位和第13位。

// function to set the register - replace <DUT>  
task load_counter ( reg [24:0] val );
#1 <DUT>.q = val ; //delay is to overwrite the main counter
endtask

或

// function to set the counter bit - replace <DUT>
task count_up  ( int count,int loc , bit val);
repeat(count) @(posedge clock ) ;
#1 <DUT>.q[loc] =  val; //delay is to overwrite the main counter
endtask
// toggle bit 24 and in between toggle bit 13 based on counts.
// 100 clock is just a value it can be changes.
task count_24( int count_24,int count_13);
repeat (count_24)
        begin
        repeat(count_13)
        begin
                count_up ( 100,13,1);
                count_up ( 100,13,0);
        end
        count_up ( 1,24,1);
        repeat(count_13)
        begin
                count_up ( 100,13,1);
                count_up ( 100,13,0);
        end
        count_up ( 1,24,0);
end
endtask

第一个方法

load_counter(25'hff0);// load and wait for bit 13 to be set 
repeat(50)  @(posedge clock ) ;
load_counter(25'h1ff0); // load and wait for bit 13 to be re-set. 
repeat(50)  @(posedge clock ) ;
load_counter(25'hf0ff0); //load and wait for bit 13 set ( while other bits > 13 are on )  
repeat(50)  @(posedge clock ) ;
load_counter(25'hfffff0); // bit 24 set 
repeat(50)  @(posedge clock ) ;
// if needed add set/reset for bit 13 code here 
load_counter(25'h1fffff0); // load and wait till bit 24 rolls over 
repeat(50)  @(posedge clock ) ; 
 // repeat the whole process above in a loop to get desired behavior

您还可以随机化需要在每个24位切换之间看到的13位切换的数量和需要在计数器变化之间运行的时钟数量。

方案2

13和24的计数可以由测试编写者决定，也可以随机化。

count_24(10,10)

在选项1中，我们让计数器机制完成大部分任务，因此首选。

但是最后最好运行完整的计数器来查看结果。也许你可以把它作为周末回归运行。

还可以直接观察TB中的信号。

wire [3:0] observe_unidad = <DUT>.unidad;
wire [3:0] observe_decena = <DUT>.decena;

在这里添加tb的完整代码…

// this code will not synthesize
module tb_cont ;

reg clock_gen ; // To generate a clock
reg reset_gen ; // to generate reset
// Main counter instance
cont  cont_instance (
                .clock(clock_gen),
                .reset ( reset_gen)
                ) ;
// Clock generation block
initial
begin
clock_gen = 0 ;
forever
begin
        #10 clock_gen = 0 ;
        #10 clock_gen = 1 ;
end
end
// Task to write data in the cont- block
task count_up  ( int count,int loc , bit val);
repeat(count) @(posedge clock_gen ) ;
#1  cont_instance.q[loc] =  val; //delay is to overwrite themain counter
endtask
/ toggle bit 24 and in between toggle bit 13 based on counts.
// 100 clock is just a value it can be changed.
task count_24( int count_24,int count_13);
repeat (count_24)
        begin
        repeat(count_13)
        begin
                count_up ( 100,13,1);
                count_up ( 100,13,0);
        end
        count_up ( 1,24,1);
        repeat(count_13)
        begin
                count_up ( 100,13,1);
                count_up ( 100,13,0);
        end
        count_up ( 1,24,0);
end
endtask
// task to load the counter
task load_counter ( reg [24:0] val );
#1 cont_instance.q = val ; //delay is to overwrite themain counter
endtask

initial
begin 
// dump  waveform to observe signals
$dumpvars;
// generate a reset first
reset_gen = 0 ;  
#100 reset_gen = 0 ;
#100 reset_gen = 1 ;
#100 ;
@(posedge clock_gen ) ;
reset_gen = 0 ;
end
// value for the count
int count13 = 100;
int count24=100;
// generate test vector
initial
begin
repeat( 100 ) @ ( posedge clock_gen ) ; // wait for counter
load_counter(25'hff0);
repeat( 100 ) @ ( posedge clock_gen ) ; // wait for counter
load_counter(25'hfffff0); 
repeat( 100 ) @ ( posedge clock_gen ) ; // wait for counter
load_counter(25'h1fffff0);
repeat( 100 ) @ ( posedge clock_gen ) ; // wait for counter
// scheme 2 
count_24(10,10);
$finish ;
end
// both the signal can eb observed 
wire [3:0] observe_unidad = cont_instance.unidad;
wire [3:0] observe_decena = cont_instance.decena;
endmodule