在 Nexys4 DDR 板上使用 Verilog 执行 FIFO

Question

>模拟输出

您好，请帮助我解决这个问题。使用下面给出的代码 buff_mem.v

在模拟之前一切正常，但是当我尝试在船上编程(Nexys4 DDR(时出现问题。只需一次推送和一次弹出即可显示完整和空标志，而我想将数据写入其深度(即直到 fifo_counter = f(。我想写入多个数据直到其深度(满(，然后读取直到其空。..这不会发生。是按钮一次按多次写入和读取的问题，还是我不知道???PLIZ帮助我处理代码!!

`define BUF_WIDTH 4    
`define BUF_SIZE ( 1<<`BUF_WIDTH )
module buff_mem( clk, rst, wr_en, rd_en, buf_in, buf_out, buf_empty, buf_full, fifo_counter );
input                 rst, clk, wr_en, rd_en;   
input [7:0]           buf_in;                   
output[7:0]           buf_out;                  
output                buf_empty, buf_full;      
output[(`BUF_WIDTH - 1):0] fifo_counter;             
reg[7:0]              buf_out;
reg                   buf_empty, buf_full;
reg[(`BUF_WIDTH - 1):0]  fifo_counter;
reg[(`BUF_WIDTH - 1):0]  rd_ptr, wr_ptr;        // pointer to read and write addresses  
reg[7:0] buf_mem [`BUF_SIZE - 1 : 0];           // RAM  
always @(fifo_counter)
begin
   buf_empty = (fifo_counter==0);
   buf_full = (fifo_counter==(`BUF_SIZE - 1));
end
always @(posedge clk or posedge rst)
begin
   if( rst )
       fifo_counter <= 0;
   else if( (!buf_full && wr_en) && ( !buf_empty && rd_en ) )
       fifo_counter <= fifo_counter;
   else if( !buf_full && wr_en )
       fifo_counter <= fifo_counter + 1;
   else if( !buf_empty && rd_en )
       fifo_counter <= fifo_counter - 1;  
   else
      fifo_counter <= fifo_counter;
end
always @( posedge clk or posedge rst)       //read
begin
   if( rst )
      buf_out <= 0;
   else
   begin
      if( rd_en && !buf_empty )
         buf_out <= buf_mem[rd_ptr];
      else
         buf_out <= buf_out;
   end
end
always @(posedge clk)                   //write
begin
   if( wr_en && !buf_full )
      buf_mem[ wr_ptr ] <= buf_in;
   else
      buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always@(posedge clk or posedge rst)     //handling rd_ptr & wr_ptr
begin
   if( rst )
   begin
      wr_ptr <= 0;
      rd_ptr <= 0;
   end
   else
   begin
      if( !buf_full && wr_en )    wr_ptr <= wr_ptr + 1;
        else  wr_ptr <= wr_ptr;
      if( !buf_empty && rd_en )   rd_ptr <= rd_ptr + 1;
        else rd_ptr <= rd_ptr;
   end
end
endmodule

这是它的约束文件 -

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRfifo_counter5 Sch=clk100mhz
##Switches
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { wr_en }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { rd_en }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { buf_in[0] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { buf_in[1] }]; #IO_L13N_T2_MRwr_en4 Sch=sw[3]
set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { buf_in[2] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { buf_in[3] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { buf_in[4] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { buf_in[5] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { buf_in[6] }]; #IO_L24N_T3_34 Sch=sw[8]
set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { buf_in[7] }]; #IO_25_34 Sch=sw[9]
## LEDs
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { buf_empty }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { buf_full }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { buf_out[0] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { buf_out[1] }]; #IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { buf_out[2] }]; #IO_L7P_T1_D09_14 Sch=led[4]
set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { buf_out[3] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { buf_out[4] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { buf_out[5] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { buf_out[6] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { buf_out[7] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
##Buttons
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L9P_T1_DQS_14 Sch=btnc
set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { wr_en }]; #IO_L4N_T0_D05_14 Sch=btnu
set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { rd_en }]; #IO_L12P_T1_MRCC_14 Sch=btnl

Answer 1

按钮需要一个去抖电路。这是Verilog中的一个例子，但是我自己还没有尝试过。每个按钮应该有一个此模块的实例(例如 CC_1，rd_en(。

要查看按下按钮时发生了什么，CC_3也可以连接到 LED。据我从电路板原理图上看到，有可用的LED。

LED10 -> U14
LED13 -> V14
LED14 -> V12
LED15 -> V11