如何在其他模块中连接其他模块的输入端口

Question

我试图用 https://forums.xilinx.com/t5/Embedded-Development-Tools/bidirectional-tristate-in-out-port-in-Vivado/td-p/352239 来理解verilog，尤其是inout端口。

为了理解，我已经实现了如下。但是我认为我在tb模块中使用" my_top"模块有问题

如何在"tb"模块中的"my_top"模块之间连接？我还想使用初始语句测试 tb 模块中的 my_top 模块。

如何连接以查看 TB 模块中my_top模块的工作情况？

module tb;
reg     data_tri;
reg     data_tx;
reg     data_rx;
wire    data_io;

my_top u_my_top(
  .data_tri (   data_tri            ),
  .data_tx  (   data_tx         ),
  .data_rx  (   data_rx         ),
  .data_io  (   data_io         )
  );
initial begin
#30 
//inout write 
data_tri = 0; 
data_tx = 1; 
//inout read 
data_tri = 1; 
data_io = 1;
end
endmodule

module my_top (
  input  data_tri,
  input  data_tx,
  output data_rx,
  inout  data_io
  );
assign data_io = (data_tri) ? 1'bZ : data_tx;
assign data_rx = data_io;
endmodule

Answer 1

您需要在

测试平台中以与设计中完全相同的方式驱动三态信号(使用导线(：

assign data_io = (data_tri) ? data_txtb : 1'bZ;

因此，例如：

module tb;
reg     data_tri;
reg     data_tx;
reg     data_txtb;
wire    data_rx;
wire    data_io;
  my_top u_my_top(
    .data_tri (   data_tri        ),
    .data_tx  (   data_tx         ),
    .data_rx  (   data_rx         ),
    .data_io  (   data_io         )
  );
  assign data_io = (data_tri) ? data_txtb : 1'bZ;
  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    //inout write 
    data_tri = 0; 
    data_tx = 1; 
    #30 
    data_tx = 0; 
    #30 
    data_tx = 1; 
    #30 
    //inout read 
    data_tri = 1; 
    data_txtb = 0; 
    #30 
    data_txtb = 1; 
    #30 
    data_txtb = 0; 
    #30; 
  end
endmodule

https://www.edaplayground.com/x/342E