在linux内核的内存屏障文档(documentation/memory-barrier .txt)中，有一些例子表明，在内存屏障之后的写入器在其他cpu的内存屏障之前是可见的。这是怎么发生的?为什么写屏障不足以对这些写进行排序?
特别是以下内容:
843 CPU 1 CPU 2
844 ======================= =======================
845 { B = 7; X = 9; Y = 8; C = &Y }
846 STORE A = 1
847 STORE B = 2
848 <write barrier>
849 STORE C = &B LOAD X
850 STORE D = 4 LOAD C (gets &B)
851 LOAD *C (reads B)
852
853 Without intervention, CPU 2 may perceive the events on CPU 1 in some
854 effectively random order, despite the write barrier issued by CPU 1:
855
856 +-------+ : : : :
857 | | +------+ +-------+ | Sequence of update
858 | |------>| B=2 |----- --->| Y->8 | | of perception on
859 | | : +------+ +-------+ | CPU 2
860 | CPU 1 | : | A=1 | --->| C->&Y | V
861 | | +------+ | +-------+
862 | | wwwwwwwwwwwwwwww | : :
863 | | +------+ | : :
864 | | : | C=&B |--- | : : +-------+
865 | | : +------+ | +-------+ | |
866 | |------>| D=4 | ----------->| C->&B |------>| |
867 | | +------+ | +-------+ | |
868 +-------+ : : | : : | |
869 | : : | |
870 | : : | CPU 2 |
871 | +-------+ | |
872 Apparently incorrect ---> | | B->7 |------>| |
873 perception of B (!) | +-------+ | |
874 | : : | |
875 | +-------+ | |
876 The load of X holds ---> | X->9 |------>| |
877 up the maintenance +-------+ | |
878 of coherence of B ----->| B->2 | +-------+
879 +-------+
880 : :
881
882
883 In the above example, CPU 2 perceives that B is 7, despite the load of *C
884 (which would be B) coming after the LOAD of C.
写屏障使正确地安排写。
如下文所述，问题是CPU 2可以在C之前读取*C，因为它没有使用任何类型的读屏障。
关于内存障碍的更好的文章是http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf