状态转换取决于输入事件VHDL

Question

我是VHDL中的新手。我目前正在开发FSM，我希望我的状态机才能在输入更改时更改状态。我应该在以下代码中进行什么更改？

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           x_in : in STD_LOGIC;                         -- input Bitstream  
           y_out : out STD_LOGIC_VECTOR (1 downto 0));  -- Encoded output
end fsm;
-----------------------------------------------------
architecture Behavioral of fsm is
  -- Building an Enumerated type for the state machine
  type state_type is (s_idle,s1,s2,s3,s4);  -- constraint length = 3, Hence number of Regs = 2 therefore Number of states = 4
  signal state, next_state: state_type ;    -- Registers to hold the Present and next states
begin
-----------------------------------------------------
  process1: process (reset, clk)             --  Sequential Logic Selection process:
     begin
          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 1

假设您想在 ->

时使FSM更改状态

1. clk高
2. X_in更改的值

另外，我假设您的next_state变量是state的某些组合函数，您尚未提及。只有一个更改就足够了，将X_in添加到您的过程灵敏度列表中。

-----------------------------------------------------
  process1: process (X_in, reset, clk)             --  Sequential Logic Selection process:
     begin
          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 2

假设x_in输入与clk同步，这将执行您描述的内容：

 process1: process (reset, clk)
 begin
      if (reset ='1') then  
          state <=s_idle;         
      elsif (clk='1' and clk'Event) then
          x_in_prev <= x_in;
          if x_in_prev /= x_in then
              state <= next_state;
          end if;
      end if;
 end process process1;

您需要在体系结构中定义x_in_prev信号才能进行编译。