Verilog.将输出设置为连续剧加法器中的输入

Question

我不久前就开始了Verilog，并且在我的Ripple Adder中遇到了一些有条件的语句。我有一个6位波纹加法器（可行），但我想添加一个额外的功能。我有一个2位变量，称为'Changer';

if changer == 00, then display input1
if changer == 01, then display input2
else display the summation result.

这是我拥有的。

`timescale 1ns/10ps
module SixBitRippleAdder(
    input [5:0] x, //Input 1
    input [5:0] y, //Input 2
    input sel, //Add or subtract switch
    input [1:0] changer, //Condition switch
    output overflow,
    output [5:0] sum
    );
    reg [5:0] w;
    wire [5:0] c_out; //Used for carries
    //6 bit adder by adding instantiating 6 1 bit adders
    FullAdder bit1(.a(x[0]), .b(y[0] ^ sel), .s(sum[0]), .cin(sel), .cout(c_out[0]));
    FullAdder bit2(.a(x[1]), .b(y[1] ^ sel), .s(sum[1]), .cin(c_out[0]), .cout(c_out[1]));
    FullAdder bit3(.a(x[2]), .b(y[2] ^ sel), .s(sum[2]), .cin(c_out[1]), .cout(c_out[2]));
    FullAdder bit4(.a(x[3]), .b(y[3] ^ sel), .s(sum[3]), .cin(c_out[2]), .cout(c_out[3]));
    FullAdder bit5(.a(x[4]), .b(y[4] ^ sel), .s(sum[4]), .cin(c_out[3]), .cout(c_out[4]));
    FullAdder bit6(.a(x[5]), .b(y[5] ^ sel), .s(sum[5]), .cin(c_out[4]), .cout(c_out[5]));
    assign overflow = c_out[5] ^ c_out[4];
    //Issue is with these conditions
    always @*
        begin
            if(changer == 2'b00)
                w = x;
            else if(changer == 2'b01)
                w = y;
            else
                w = sum;
        end
    assign sum = w;
endmodule

我正在尝试综合这个问题，但是我的始终障碍有错误。错误是"多个驱动器网"

非常感谢

Answer 1

我想您只需要一个不同的变量，这将是总结的结果：

wire [5:0] sumTmp;

然后

FullAdder bit1(.a(x[0]), .b(y[0] ^ sel), .s(sumTmp[0]), .cin(sel), .cout(c_out[0]));
                                            ^^^^^^^^^
    ...

及以后：

always @*
    begin
        if(changer == 2'b00)
            w = x;
        else if(changer == 2'b01)
            w = y;
        else
            w = sumTmp;
    end
assign sum = w;