嗨，棒极了的stackoverflow社区，
我正在为我的学校做一个项目，我必须一个接一个地打开不同的LED，才能在Xilinx Spartan3E-100上制作一个"旋转灯"。目前，我的VHDL程序可以工作，但没有时钟，所以所有的LED都打开了（太快）。当我尝试添加时钟时，我得到以下错误：
The signal <CLK_IBUF> is incomplete. The signal does not drive any load pins in the design.
这是我的VHDL代码（经过编辑）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test2 is
Port ( CLK : in STD_LOGIC;
S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_LOGIC;
S4 : out STD_LOGIC;
S5 : out STD_LOGIC;
S6 : out STD_LOGIC);
end test2;
architecture Behavioral of test2 is
CONSTANT st0 : std_logic_vector(0 TO 2) := "000"; -- listing case for signal
CONSTANT st1 : std_logic_vector(0 TO 2) := "001";
CONSTANT st2 : std_logic_vector(0 TO 2) := "010";
CONSTANT st3 : std_logic_vector(0 TO 2) := "011";
CONSTANT st4 : std_logic_vector(0 TO 2) := "100";
CONSTANT st5 : std_logic_vector(0 TO 2) := "101";
CONSTANT st6 : std_logic_vector(0 TO 2) := "110";
SIGNAL state : std_logic_vector(0 TO 2) := "000";
BEGIN
chenillard: PROCESS(CLK)
BEGIN
if (rising_edge(CLK)) then -- synchronise clock for the following case
case state is
when st0 => -- when signal is 000
S0<='1'; -- it will switch on a led.
state<=st1; -- signal incrementation
when st1 => -- when signal is 001
S1<='1'; -- it will switch on a led.
state<=st2; -- signal incrementation
when st2 => -- when signal is 010
S2<='1'; -- it will switch on a led.
state<=st3; -- signal incrementation
when st3 => -- when signal is 011
S3<='1'; -- it will switch on a led.
state<=st4; -- signal incrementation
when st4 => -- when signal is 100
S4<='1'; -- it will switch on a led.
state<=st5; -- signal incrementation
when st5 => -- when signal is 101
S5<='1'; -- it will switch on a led.
state<=st6; -- signal incrementation
when st6 => -- when signal is 110
S6<='1'; -- it will switch on a led.
state<=st0; -- signal incrementation back to st0 for loop
when others =>NULL;
end case;
end if;
end process chenillard;
end Behavioral;
这是我的UCF文件：
NET "CLK" LOC = "C8";
NET "S0" LOC= "M5";
NET "S1" LOC= "M11";
NET "S2" LOC= "P7";
NET "S3" LOC= "P6";
NET "S4" LOC= "N5";
NET "S5" LOC= "N4";
NET "S6" LOC= "P4";
我在谷歌上搜索答案，但似乎没有找到任何答案。谢谢你的帮助，对我的英语感到抱歉，我不是以英语为母语的人；）
终于成功了！我注意到该程序创建的真值表与我的理论真值表不同。以下是该程序创建的新真值表：真值（_T）
以下是我解决问题的方法：
if (rising_edge(CLK)) then -- synchronise clock for the following case
case state is
when st0 => -- when signal is 000
S0<='1'; -- it will switch on a led.
S1<='0';
S2<='0';
S3<='0';
S4<='0';
S5<='0';
S6<='0';
state<=st1; -- signal incrementation
when st1 => -- when signal is 001
S1<='1'; -- it will switch on a led.
S0<='0';
S2<='0';
S3<='0';
S4<='0';
S5<='0';
S6<='0';
state<=st2; -- signal incrementation
when st2 => -- when signal is 010
S2<='1'; -- it will switch on a led.
S0<='0';
S1<='0';
S3<='0';
S4<='0';
S5<='0';
S6<='0';
state<=st3; -- signal incrementation
when st3 => -- when signal is 011
S3<='1'; -- it will switch on a led.
S0<='0';
S1<='0';
S2<='0';
S4<='0';
S5<='0';
S6<='0';
state<=st4; -- signal incrementation
when st4 => -- when signal is 100
S4<='1'; -- it will switch on a led.
S0<='0';
S1<='0';
S2<='0';
S3<='0';
S5<='0';
S6<='0';
state<=st5; -- signal incrementation
when st5 => -- when signal is 101
S5<='1'; -- it will switch on a led.
S0<='0';
S1<='0';
S2<='0';
S3<='0';
S4<='0';
S6<='0';
state<=st6; -- signal incrementation
when st6 => -- when signal is 110
S6<='1'; -- it will switch on a led.
S0<='0';
S1<='0';
S2<='0';
S3<='0';
S4<='0';
S5<='0';
state<=st0; -- signal incrementation back to st0 for loop
when others =>NULL;
end case;
end if;
end process chenillard;
end Behavioral;
正如你所看到的，对于每种情况，我添加了每个关闭的led，而不仅仅是一个打开的led。在这样做之前，当ISE过程映射时，它告诉clk_buf是不完整的，因为并没有列出所有的可能性。