我正在尝试使用 vhdl 制作 8 位 4-1 选择器电路。有人可以帮助我这个代码有什么问题吗？

Question

这是VHDL代码。这个没有错误

library IEEE;
use IEEE.std_logic_1164.all;
entity sel4_1 is
   port( A, B, C, D : in std_logic;
     SEL        : in std_logic_vector(1 downto 0);
     outsgnl    : out std_logic );
   end sel4_1;
architecture EX1 of sel4_1 is
begin
process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;
end EX1;

---

这是具有错误

的测试台

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TESTBENCH is
end TESTBENCH;
architecture RTL of TESTBENCH is
component sel4_1
   port(A,B,C,D : in std_logic_vector(7 downto 0);
        outsgnl : out std_logic);
end component;
signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);
begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";
     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;
     wait;
   end process;
end RTL;

出现的错误是testBench.vhdl：19：27：不能将'ina'与信号接口" ina"相关联

testbench.vhdl：19：27 ：（'ina'的类型是std_logic）

testbench.vhdl：11：9 ：（信号接口的类型" ina"是std_logic_vector的子类型）

Answer 1

问题是您的实体sel4_1和组件sel_4_1不相同。您的a，b，c，d端口是第一个中的 std_logic，而第二个则是 std_logic_vector(7 downto 0)。

用您真正需要的内容更改实体（或组件），并且应该正常工作。

Answer 2

这是进行一些更正后的代码：

library IEEE;
use IEEE.std_logic_1164.all;
entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;
architecture EX1 of sel4_1 is
begin
process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;
end EX1;

---

testbench：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TESTBENCH is
end TESTBENCH;
architecture RTL of TESTBENCH is
component sel4_1
   port(A,B,C,D : in std_logic_vector(7 downto 0);
        SEL     : in std_logic_vector(1 downto 0);
        OUTSGNL : out std_logic_vector(7 downto 0));
end component;
signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);
begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";
     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;
     wait;
   end process;
end RTL;

Answer 3

作为Hakim（完全正确）建议的替代方案，有一种并发做同一件事的方法。

library IEEE;
use IEEE.std_logic_1164.all;
entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;
architecture EX1 of sel4_1 is
begin
  with SEL select
    outsgnl <= A when "00",
               B when "01",
               C when "10",
               D when others;
end EX1;

我更喜欢避免使用时钟过程以外的任何其他方法。灵敏度列表中缺少的信号将导致模拟/合成不匹配。并且保持这些敏感性清单可能会成为熊。如果需要组合过程，则列表应该很小。（是的，有VHDL-2008的all，它有帮助。）