在 VHDL 程序中找到'2'位乘法算法运算符"="的定义

Question

这是我的代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
--arithmetic functions with Signed or Unsigned values
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity booth is port(
    m: in SIGNED(6 downto 0); -- multiplicand 2's comp
    r: in SIGNED(6 downto 0); -- multiplier 2's comp
    reset: in std_logic;
    product: out SIGNED(13 downto 0);
    clk: in std_logic
);
end booth;
architecture Behavioral of booth is
COMPONENT ALU
          PORT(
                  X : IN SIGNED(15 downto 0);
                  Y : IN SIGNED(15 downto 0);       
                  Z : OUT SIGNED(15 downto 0);
                        func : IN std_logic_vector(2 downto 0)
                  );
END COMPONENT;
          SIGNAL  X : SIGNED(15 downto 0) := (others=>'0');
             SIGNAL Y : SIGNED(15 downto 0) := (others=>'0');       
          SIGNAL  Z : SIGNED(15 downto 0) := (others=>'0');
             SIGNAL func : std_logic_vector(2 downto 0) := (others=>'0');
             type stateType is (beg, two, finish);  
             signal state: stateType;
             SIGNAL  A, S, P: SIGNED(15 downto 0) := (others=>'0');
             signal count : std_logic_vector(2 downto 0) := (others=>'0');
BEGIN
    foo: ALU PORT MAP(
        X => X,
        Y => Y,
        Z => Z,
        func => func
    );

    process(clk) is begin
        if rising_edge(clk) then
                if reset = '1' then
                    A <= (others => '0'); S <= (others => '0'); P <= (others => '0'); state <= beg;
                else
                    case state is
                        when beg => 
                            A(15 downto 9) <= m;
                            A(8 downto 0) <= "0";
                            P(7 downto 1) <= r;
                            P(15 downto 8) <= "0";
                            P(0) <= '0';
                            S(15 downto 9) <= -m;
                            S(8 downto 0) <= "0";
                            state <= two;
                        when two =>
                            if P(1 downto 0) = "01" then
                                func <= "001"; -- P + A
                                X <= P;
                                Y <= A;
                                P <= Z;
                            elsif P(1 downto 0) = "10" then
                                func <= "010"; -- P - A
                                X <= P;
                                Y <= S;
                                P <= Z;
                            end if;
                            func <= "100"; -- ASR
                            X <= P;
                            P <= Z;
                            count <= count + 1;
                            if count = x"6" then
                                state <= finish;
                            end if;
                        when finish =>
                            product <= P(15 downto 1); --bit(s)???
                    end case;
                end if;
            end if;
    end process;

end Behavioral;

我在两行上收到错误，P（1 下降到 0） = "01";和 P（1 下降到 0） = "10";

找到运算符"="的"

2"定义，无法确定"="的确切重载匹配定义

知道发生了什么吗？

Answer 1

将所有显示的上下文子句替换为以下内容：

library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;

请注意，NUMERIC_STD是IEEE软件包，STD_LOGIC_ARITH是共享软件。

您遇到的问题是由于std_logic_arith具有以下重载：

function "=" (l : unsigned; r: unsigned) return boolean ;
function "=" (l : unsigned; r: signed)   return boolean ;

因此，当您尝试与文本进行比较时，它不知道文本"10"是无符号的还是有符号的。 任何时候，只要您有两种具有相同文本值的类型并且混合重载，您就有可能遇到此类问题。

NUMERIC_STD通过为匹配类型（无符号带无符号）和（带符号签名）和否（无符号带符号）提供重载来避免这些问题，反之亦然。

避免此类问题的另一种方法是使用整数重载。 请注意，逻辑的大小由数组值决定，因此请注意数组值是否足够大，否则整数将在左侧被截断。

 P(1 downto 0) = 1 ; 
 P(1 downto 0) = 2 ;

Answer 2

是的。

您似乎没有使用std_logic_unsigned，请尝试将其使用子句注释掉。 或者更好的是，还要注释掉std_logic_signed使用条款，并引入引用包numeric_std的使用子句。