VHDL，将部分std_logic_vector数组传递到实例化的端口映射中

Question

请考虑以下代码

library ieee;
use ieee.std_logic_1164.all;
package pkg is
type foo is (A, B, C);
type foo_vector is array (foo) of std_logic_vector;
end package;

实体具有以下端口的位置

library ieee;
use ieee.std_logic_1164.all;
entity baz is 
port (iInput : in foo_vector;
oOutput : out foo_vector);
end;

它由顶部模块实例化。现在的问题是我怎样才能只将部分 bar std_logic_vectors传递到 baz 实例中？尝试使用(打开(时编译失败

library ieee;
use ieee.std_logic_1164.all;
entity top is 
end;
architecture rtl of top is 
signal bar: foo_vector (open) (31 downto 0) := (others => (others => '0'));
begin
inst : entity work.baz 
port map (iInput => bar(open)(3 downto 0), --The (open) here does not work
oOutput => open);    
end;

Answer 1

使用具有要部分分配的不受约束类型的交错数组会使您的生活变得非常困难。我会说：保持简单。只需使用三个单独的数组foovec_A、foovec_B和foovec_C即可。

但是，如果您真的想要按照自己的方式进行操作，则需要添加逻辑以将所需的信号发送到单独的foo_vector。

例如

library ieee;
use ieee.std_logic_1164.all;
package pkg is
type foo is (A, B, C);
type foo_vector is array (foo) of std_logic_vector;
end package;
use work.pkg.all;
entity baz is 
port (iInput : in foo_vector;
oOutput : out foo_vector);
end;
architecture rtl of baz is begin
end architecture;
entity top is 
end;
library ieee;
architecture rtl of top is 
use ieee.std_logic_1164.all;
use work.pkg.all;
signal bar: foo_vector(open)(31 downto 0) := (others => (others => '0'));
signal bar_part: foo_vector(open)(3 downto 0);
signal output : foo_vector(open)(0 downto 0);
begin
conn : for i in foo generate
bar_part(i) <= bar(i)(3 downto 0);
end generate;
inst : entity work.baz 
port map (iInput => bar_part,
oOutput => output);    
end;

将编译(VHDL-2008 模式(。