在VHDL中产生2个时钟脉冲

Question

如何根据触发信号生成两个时钟脉冲?我在stackoverflow中找到了这段代码(它工作得很好):

get_data:process(clk, reset)
  variable idle : boolean;
begin
  if reset = '1' then
    idle := true;
  elsif rising_edge(clk) then
    clr_flag <= '0';     -- default action
    if idle then
      if flag = '1' then
        clr_flag <= '1';  -- overrides default FOR THIS CYCLE ONLY
        idle <= false;
      end if;
    else
      if flag = '0' then
        idle := true;
      end if;
    end if;
  end if;
end process;

我想知道是否有人可以帮助我产生一个标志，持续2个时钟脉冲而不是一个。

Answer 1

我要这样做:

signal s_flag, s_flag_1z : std_logic := '0';
begin
   get_data:process(clk, reset)
      variable idle : boolean;
   begin
      if reset = '1' then
         idle      := true;
         s_flag    <= '0';
         s_flag_1z <= '0';
      elsif rising_edge(clk) then
         s_flag    <= '0';     -- default action
         s_flag_1z <= s_flag;
         if idle then
            if flag = '1' then
               s_flag <= '1';  -- overrides default FOR THIS CYCLE ONLY
               idle <= false;
            end if;
         else
            if flag = '0' then
               idle := true;
            end if;
         end if;
     end if;
end process;
cl_flag <= '1' when (s_flag & s_flag_1) /= "00" else '0';

现在标志将是2个时钟周期高，只需要一个小的增加。

/本

Answer 2

可变长度脉冲是最干净和最容易的，在移位寄存器的顶部轻拍

get_data:process(clk, reset) --make sure you really want asynchronous reset
  variable pulse_line : std_logic_vector(1 downto 0); --set the width to how many clocks you want the pulse
begin
  if reset = '1' then --again make sure you really want asynchronous reset
    pulse_line := (others => '1');
  elsif rising_edge(clk) then
    if flag = '1' then
      pulse_line := (others => '1'); --reset the shift register
    else
      pulse_line := pulse_line(pulse_line'high-1 downto 0) & '0'; --push a 0 onto bottom of the shift register
    end if;
    clr_flag <= pulse_line(pulse_line'high); --tap out the top of the shift register
  end if;
end process;