C语言 如何使用yosys从高级Verilog创建Gate级Verilog

Question

我试图从C/c++语言描述的函数最初生成门级Verilog。我的C函数是一个简单的和门:

_Bool and2gate(_Bool a, _Bool b)
{
   return a && b;
}

使用Bambu-Panda工具

http://panda.dei.polimi.it/

我设法生成了这个函数的Verilog描述:

    `ifdef __ICARUS__
  `define _SIM_HAVE_CLOG2
`endif
`ifdef VERILATOR
  `define _SIM_HAVE_CLOG2
`endif
`ifdef MODEL_TECH
  `define _SIM_HAVE_CLOG2
`endif
`ifdef VCS
  `define _SIM_HAVE_CLOG2
`endif
`ifdef NCVERILOG
  `define _SIM_HAVE_CLOG2
`endif
`ifdef XILINX_SIMULATOR
  `define _SIM_HAVE_CLOG2
`endif
`ifdef XILINX_ISIM
  `define _SIM_HAVE_CLOG2
`endif

`timescale 1ns / 1ps
module ui_bit_and_expr_FU(in1, in2, out1);
  parameter BITSIZE_in1=1, BITSIZE_in2=1, BITSIZE_out1=1;
  // IN
  input [BITSIZE_in1-1:0] in1;
  input [BITSIZE_in2-1:0] in2;
  // OUT
  output [BITSIZE_out1-1:0] out1;
  assign out1 = in1 & in2;
endmodule
// Datapath RTL descrition for and2gate
`timescale 1ns / 1ps
module datapath_and2gate(clock, reset, in_port_a, in_port_b, return_port);
  // IN
  input clock;
  input reset;
  input in_port_a;
  input in_port_b;
  // OUT
  output return_port;
  // Component and signal declarations
  wire [0:0] out_ui_bit_and_expr_FU_1_1_1_3_i0_fu_and2gate_21644_21668;
  ui_bit_and_expr_FU #(.BITSIZE_in1(1), .BITSIZE_in2(1), .BITSIZE_out1(1)) fu_and2gate_21644_21668 (.out1(out_ui_bit_and_expr_FU_1_1_1_3_i0_fu_and2gate_21644_21668), .in1(in_port_a), .in2(in_port_b));
  // io-signal post fix
  assign return_port = out_ui_bit_and_expr_FU_1_1_1_3_i0_fu_and2gate_21644_21668;
endmodule
// FSM based controller descrition for and2gate
`timescale 1ns / 1ps
module controller_and2gate(done_port, clock, reset, start_port);
  // IN
  input clock;
  input reset;
  input start_port;
  // OUT
  output done_port;
  parameter [0:0] S_0 = 1'd0;
  reg [0:0] _present_state, _next_state;
  reg done_port;
  always @(posedge clock)
    if (reset == 1'b0) _present_state <= S_0;
    else _present_state <= _next_state;
  always @(*)
  begin
    _next_state = S_0;
    done_port = 1'b0;
    case (_present_state)
      S_0 :
        if(start_port != 1'b1 )
        begin
          _next_state = S_0;
        end
        else
        begin
          _next_state = S_0;
          done_port = 1'b1;
        end
      default :
        begin
          done_port = 1'b0;
        end
    endcase
  end
endmodule
// Top component for and2gate
`timescale 1ns / 1ps
module and2gate(clock, reset, start_port, done_port, a, b, return_port);
  // IN
  input clock;
  input reset;
  input start_port;
  input a;
  input b;
  // OUT
  output done_port;
  output return_port;
  // Component and signal declarations
  controller_and2gate Controller_i (.done_port(done_port), .clock(clock),        
.reset(reset), .start_port(start_port));
  datapath_and2gate Datapath_i (.return_port(return_port), .clock(clock),     
.reset(reset), .in_port_a(a), .in_port_b(b));
endmodule
// Minimal interface for top component: and2gate
`timescale 1ns / 1ps
module and2gate_minimal_interface(clock, reset, start_port, a, b, done_port, return_port);
  // IN
  input clock;
  input reset;
  input start_port;
  input a;
  input b;
  // OUT
  output done_port;
  output return_port;
  // Component and signal declarations
  and2gate and2gate_i0 (.done_port(done_port), .return_port(return_port), .clock(clock), .reset(reset), .start_port(start_port), .a(a), .b(b));
endmodule

然而，据我所知，这不是门级verilog。我想做的是创建一个单模块网络列表Verilog(具有单个模块的门级Verilog)。

我知道Yosys工具允许创建这样的Verilog。然而，我无法达到预期的输出。我想要以下格式的输出:

module top (input clk, // clock
            input rst, // reset
            input g_init, //for sequential circuits, initial value for                        
            registers from garbler. Only read in first clock cycle
input e_init, //same for evaluator
input g_input, // garbler's input
input e_input,//evaluator's input
output o // output
);

我将非常感谢如何从上面的更高级别verilog生成这种Gate Level代码的解释，无论是使用Yosys还是其他合成和sim工具。

我也将感谢任何关于如何从C代码生成Verilog的建议，以及哪些工具被推荐用于这样的任务?

Answer 1

我已经将verilog代码复制到一个文件(and2gate.v)并运行以下yosys命令行:

yosys -p 'synth -flatten -top and2gate; clean -purge; write_verilog -noattr and2gate_syn.v' and2gate.v

这会产生以下输出文件(and2gate_syn.v):

/* Generated by Yosys 0.6+337 (git sha1 81bdf0a, clang 3.8.0-2ubuntu4 -fPIC -Os) */
module and2gate(clock, reset, start_port, done_port, a, b, return_port);
  input a;
  input b;
  input clock;
  output done_port;
  input reset;
  output return_port;
  input start_port;
  assign return_port = b & a;
  assign done_port = start_port;
endmodule

请参阅yosys命令的输出，例如help synth和help write_verilog，以了解该脚本中使用的各个命令的描述。

Gate Level Verilog with a single module

通常术语"门级"用于已映射到标准单元库的设计。但是，您没有提供要映射到的标准单元库。我认为上述解决方案是尽可能接近门级设计，而无需实际映射到单元库。