我想用计数器生成延迟，实际上在这里，我用计数器在每次1位传输后生成延迟，这样它就可以更好地从外部了解通过SPI（串行）LCD连接的fpga引脚。因此，我创建了一个移位寄存器，它先移位1位，然后给出延迟，然后再给出下一位（位延迟位延迟..）。
这是我的计数器代码：
module spidelay(
input wire clk,
input wire enb,
output reg sclkout
);
reg [23:0] stmp;
always @(posedge clk) begin
if ( enb == 1 ) begin
stmp = stmp+1;
if( stmp[23] == 1 ) begin
sclkout = 1'b1;
stmp = 24'b0;
end
end
else begin
stmp = 24'b0;
sclkout = 1'b0;
end
end
endmodule
朋友们，但问题是我不知道如何在always block内部启用/启动计数器。我的意思是，我不知道我们如何在想要始终在内部产生延迟的线路上启动/启用计数器。
现在这是我的Top模块的代码，我想从中生成特定行的延迟--->>
module Nokia_LCD(input clk,input switch,output OUT,output reset,inout sck,output cs);
wire clk;//On Board Clock
wire switch;//Switch For RESET
integer i;
integer z;//Used for, for loop for generating delay
reg signed OUT;//OUT for sending Data serially to LCD
reg reset=1'b1;//To Reset LCD
wire sck; //We select sck as inout because it taking input from counter Instance and then gives output to LCD..
reg cs; //Chip select pin of lcd always set to zero
reg signed[8:0]out;//Register for Storing value of OUT
reg [5:0]state =6'b000000; //Initialize states to Zero
reg [7:0]finder; //Finder finds the state that was last present in it so that by this we again go to that state sequentially
reg [7:0]font[1:0][5:0];//2-D Array of 8 Bit For Font
reg [23:0]stmp=24'b00000_00000_00000_00000_0000;
reg enb;
wire sclkout;
counter count1(clk,sck);//Instance of Counter1 for SCK Clock
spidelay count2(clk,enb,sclkout);
always@(posedge clk)
begin
case (state)
/* Lcd Initialization starts from here*/
6'b000000 : begin
finder=8'b00000000;
cs=1'b0;
out=9'b0_00010001; //Using Command SLEEPOUT (Hex 0x11) - Exits LCD sleep mode
state=6'b010001;
end
6'b000001: begin
finder=8'b00000001;
cs=1'b0;
out=9'b0_00000011; //Using Command BSTRON (Hex 0x03) - Turns on booster voltage
state =6'b010001;
end
/******************************************************************************************************************/
/************************************ State for SPI Data Transfer & Delay *****************************************/
/******************************************************************************************************************/
6'b010001:begin
//We Use finder to find the state from which it Comes...
if(finder==8'b00000000) //for 0
begin:close1
cs=1'b0;
for(i=0;i<=8;i=i+1)
begin
out=out<<<1;
OUT=out[8];
enb=1'b1; <<<<<<<-----|This is the place where I want it to enable counter and it must stop here for counting and during this time it not move for othe count of for loop......
if(stmp[23]==1'b1)
begin
disable close1;
end
end
state=6'b000001;//Go to State 000001(BSTRON)
end
endcase
end //Always end
endmodule
必须注意的是，《老友记》对我进行了编辑，以便集中精力处理错误点。。。。因此，如果你在某个地方发现语法错误，请忽略它，但请帮助我，并给出一些建议，通过给出enb=1'b1来在Toppest模块的总是块上生成延迟。。。。。。。
建议在边缘触发块always @( posedge ... 内部使用<=
你提到的延迟我想你指的是延迟固定数量的时钟周期。在这种情况下，这就是你所做的，你只是在不满足计数器要求时没有重置sclkout。
if ( enb == 1 ) begin
sclkout <= 1'b0; //Reset by default
stmp <= stmp+1;
if( stmp[23] == 1 ) begin //Counter target
sclkout <= 1'b1;
stmp <= 24'b0;
end
end
else begin
//...
或者添加else
if ( enb == 1 ) begin
if( stmp[23] == 1 ) begin //Counter target
sclkout <= 1'b1;
stmp <= 24'b0;
end
else begin
sclkout <= 1'b0; //Reset by default
stmp <= stmp+1;
end
end
else begin
//...
注意：输入是隐式连接，如果你不想写，你不必写。input wire clk和input clk是一样的。
我还想在比较中添加一个宽度，即== 1'b0而不是== 0，否则在稍后的设计流程中，您将收到宽度不匹配的警告。
更新
根据注释中添加的信息，要求计数器在enb==1'b1时停止，我假设它代表"启用条"
always @ (posedge clk) begin
if ( enb == 1'b0 ) begin
// When enable bar is low this is Active
stmp <= stmp + 1'b1;
// etc ...
end
//else begin
// Do Nothing (hold state)
//end
end