Verilog旧价值观问题

Question

我几乎完成了在FPGA板上实现5级流水线Mips Cpu (Spartan 3E starter kit)。但是有一个模块有一个严重的问题。

这个问题是当模块从输入信号中取数据时，模块取旧值。这个模块就是寄存器，它是CPU最重要的部分。

这是截图(Isim):截图http://cfile8.uf.tistory.com/original/2441AB3351B74AD217FE01

灰色箭头是我设计的(我想要的)。

但模块工作为红色箭头。

模块定义

(When reg_write is true) and (Clk is true-not show in screenshot)
register[write_reg]=write_data;

我有我自己的FPGA板(Spartan 3E starter kit)

我只在船上实现了这个模块。我用板载sw0~4制作了signal(Clk, signal. write_reg, write_data)。(即使是clk)

然后它工作了!

没有问题。

，但在整个CPU设计中使用该模块。

模块出现旧值问题

这是整个源代码

module reg1(Reset, Clk, read_reg1, read_reg2, write_reg, write_data, reg_write, read_data1, read_data2
);
 input Reset;
 input Clk;
 input reg_write;
input [4:0] read_reg1, read_reg2, write_reg; 
 input [31:0] write_data;    
 output [31:0] read_data1;
 output [31:0] read_data2;
 reg [31:0] register [11:0];     
 reg [31:0] read_data1_reg;
reg [31:0] read_data2_reg;
 wire [31:0] read_data1=read_data1_reg;
 wire [31:0] read_data2=read_data2_reg;
always @(reg_write or Reset or read_reg1 or read_reg2)
 begin
 if(reg_write == 1'b0 )
  begin
    case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase
    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
  end
 else
 begin
    if(Clk==1'b1)
        case(write_reg)
        5'b00000: register[0] = write_data;
        5'b00001: register[1] = write_data;
        5'b00010: register[2] = write_data;
        5'b00011: register[3] = write_data;
        5'b00100: register[4] = write_data;
        5'b00101: register[5] = write_data;
        5'b00110: register[6] = write_data;
        5'b00111: register[7] = write_data;
        5'b01000: register[8] = write_data;
        5'b01001: register[9] = write_data;
        5'b01010: register[10] = write_data;
        5'b01011: register[11] = write_data;
        default: register[0] = register[0];
        endcase
else
    begin
    //read_data1_reg = register[read_reg1];
    //read_data2_reg = register[read_reg2];
    case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase
    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
    end
 end

  if(Reset)
     begin
     register[0] = 32'h00000000;
     register[1] = 32'h00000000;
     register[2] = 32'h00000000;
     register[3] = 32'h00000000;
     register[4] = 32'h00000000;
     register[5] = 32'h00000000;
     register[6] = 32'h00000000;
     register[7] = 32'h00000000;
     register[8] = 32'h00000000;
     register[9] = 32'h00000000;
     register[10] = 32'h00000000;
     register[11] = 32'b00000000000000000000000110010000;

     case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase
    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
     //
     end
    else
    begin
    register[0] = register[0];
    register[1] = register[1];
    register[2] = register[2];
    register[3] = register[3];
    register[4] = register[4];
    register[5] = register[5];
    register[6] = register[6];
    register[7] = register[7];
    register[8] = register[8];
    register[9] = register[9];
    register[10] = register[10];
    register[11] = register[11];
            case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase
    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
    end
  end

endmodule

Answer 1

第一个问题，clk不在always块的敏感性列表中，但您在其中一个if语句中使用它。

更值得关注的是这整个块的编码。当您需要寄存器时，您正在推断锁存器。首先要纠正的是，当您想要非阻塞赋值"<="时，您正在使用阻塞赋值"="。你应该考虑改变的第二件事是取出寄存器赋值并在不同的always块中完成。它看起来像这样:

always@(posedge clk, posedge reset)
begin 
    if(reset)
        reset data
    else if( write_en0
        set regs to writedata
    else 
        reg <= reg 
end 
always@(posedge clk, posedge reset)
begin 
    read_data1 data
end 
always@(posedge clk, posedge reset)
begin 
    read_data2 data
end 

这篇论文解释得很好:http://www-inst.eecs.berkeley.edu/cs152/fa04/救济/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf