使用案例陈述的JK触发器的VHDL程序

Question

library ieee;
use ieee. std_logic_1164.all;
entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin
process(clock,j,r)
begin
jk <= j & k;
if(clock= '1' and clock'event) then
case (jk) is
when "00" => temp<= temp;
when "01" => temp <= '0';
when "10" => temp <= '1';
when "11" => not temp;
when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;
end behavioral;

当我使用 ghdl 编译此程序时，它显示错误"何时"而不是"不"。请帮助我找到此代码的问题。

Answer 1

你忘记了这些事情：

1(when "11" => not temp;到when "11" => temp <= not temp;

2(when others => temp <= 'X'末尾必须有分号when others => temp <='X';

3(您在IF结束时错过了end if

4(过程灵敏度列表包含一个名为"r"的信号，该信号未声明

我省略了进程中的信号 j 和 k，因为您在 if 语句中执行的所有代码仅受时钟条件，因此当 j 和 k 更改其值并且时钟不在上升沿时，无需执行该过程。

library ieee;
use ieee. std_logic_1164.all;
entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin
process(clock)
begin
jk <= j & k;
if(clock= '1' and clock'event) then
case (jk) is
when "00" => temp<= temp;
when "01" => temp <= '0';
when "10" => temp <= '1';
when "11" => temp <= not temp;
when others => temp <= 'X';
end case;
end if;
end process;
q <= temp;
qbar <= not temp;
end behavioral;