如果控制语句，则Verilog语法错误

Question

我正在尝试在Verilog中为我的几个不同选择的模块制作零检查模块。

module check_zero (input [63:0] a, b, [1:0] select, output reg [63:0] out);
if ((a[51:0] == 0) && (b[51:0] == 0)) begin  
          out <= 0;
          state <= done;
end else if (a[51:0]==0 && select==0) begin
      out <= b;
          state <= done;
end else if (b[51:0]==0 && select==0) begin
      out <= a;
          state <= done;
end else if (a[51:0]==0 && select==1) begin
      out[63] <= ~b[63];
      out[62:0] <= ~b[62:0];
          state <= done;
end else if (b[51:0]==0 && select==1) begin
      out <= a;
          state <= done;
end else if (a[51:0]==0 && select==2) begin
      out <= 0;
          state <= done;
end else if (b[51:0]==0 && select==2) begin
      out <= 0;
          state <= done;
end
end else if (a[51:0]==0 && select==3) begin
      out <= 0;
          state <= done;
end else if (b[51:0]==0 && select==3) begin
        out[63] <= 1;
            out[62:52] <= 2047;
            out[51] <= 1;
            out[50:0] <= 0;
            state <= done;
end
endmodule

我在Modelsim中遇到2个错误： 1.(vlog-13069(语法错误，出现在第2行中的意外'＆lt; =' 2.(vlog-13205(在以下范围中发现的语法错误，是否缺少'::'

Answer 1

您在那里有一个额外的"结尾"。

 end else if (b[51:0]==0 && select==2) begin
 out <= 0;
 state <= done;
 end // this is extra, delete it