VHDL中的5秒计时器

Question

我在FPGA中使用50MHz时钟，并尝试制作5秒的计时器。在CNT_T以下达到5 x 50MHz(x" 0EE6B280" -> 250,000,000(，然后将time_tick_32至1进行，然后制作cnt_t＆lt; = x" 00000000";。下面的代码不起作用，从不time_tick_32获取1。

signal cnt_t    : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
signal time_tick : STD_LOGIC:= '0' ;
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000";

process (clk_50) IS
    begin
      if falling_edge(clk_50)  then
      cnt_t <= cnt_t + '1';
      end if;
    if (cnt_t = x"0EE6B280") then --if 5 seconds  
        time_tick <= '1';
        cnt_t <= x"00000000";
        time_tick_32(0)<=time_tick;
    else
        time_tick <= '0';
        time_tick_32(0)<=time_tick;
    end if;
end process;

Answer 1

尝试：

signal cnt_t    : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
signal time_tick : STD_LOGIC:= '0' ;
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000";

-- I assume you begin your architecture somewhere
-- Can make the following a concurrent statement
-- (unless it is some kind of shift reg assigned in a diff process...
-- then you will get multiple driver issues)
time_tick_32(0) <= time_tick;
process (clk_50) IS
begin
    if rising_edge(clk_50)  then -- Changed to rising_edge; 
                                -- Any particular reason you are using falling_edge?
        if (cnt_t = x"0EE6B280") then --if 5 seconds  
            time_tick <= '1';
            cnt_t <= x"00000000";
        else
            time_tick <= '0';
            cnt_t <= cnt_t + '1';  
        end if;
    end if;
end process;