如何在Verilog中定义参数模块

Question

i在Verilog中的模块下方有延迟延迟：

  module DelayModule (input_signal, delayed_signal);
    output  delayed_signal;
    input input_signal;
    wire [16:1] dummy_wire;
    wire [16:1] other = {dummy_wire[15:1],input_signal};
    assign delayed_signal =  dummy_wire[16];
    BUFX12 BUF [16:1] (.A(other),.Y(dummy_wire));
  endmodule

我想制作此模块，以便使用输入参数我可以根据输入参数延迟此模块变量。这样的东西：

module DelayModule (input_signal, delayed_signal,k);
    output  delayed_signal;
    input input_signal;
    integer k;
    wire [k:1] dummy_wire;
    wire [k:1] other = {dummy_wire[k-1:1],input_signal};
    assign delayed_signal =  dummy_wire[k];
    BUFX12 BUF [k:1] (.A(other),.Y(dummy_wire));
endmodule

在Verilog中不允许此声明，但是我正在寻找一种实现这样的技术，使模块接受某些参数，例如k，但模块内部模块中的buffer and tire norues是该k值的参数。我想知道我是否可以做这样的事情或做某事以在Verilog中实现此想法？

Answer 1

仅通过Verilog参数允许(通常以层次参数的形式实现，将其实例化的目标模块传递到目标模块(。请注意，这将是编译时间选项，因此您将无法在控制器操作期间更改它。以下是代码段，解释了此概念：

//----------------------------------------------------
// Module Name: dff_sync.v
//----------------------------------------------------
// Description: conventional 2xFF sync module with parameterizable options
//              such as:
//              - (1) Reset Value - DFF_SYNC_RESET_VALUE
//              - (2) Number of FF stages - DFF_SYNC_NUM_FF_STAGES
//              - (3) Input Bus width - DFF_SYNC_INP_BUS_WIDTH
//
// TBD:
//     - application of random delay (+/- 1 clk cycle), as it is the best evidence
//       of bug-free CDC functinal implementation.
//----------------------------------------------------
module dff_sync #
(
    parameter DFF_SYNC_RESET_VALUE   = 'b0,
    parameter DFF_SYNC_NUM_FF_STAGES = 'd2,
    parameter DFF_SYNC_INP_BUS_WIDTH = 'd1
)
(
    input                               clk,
    input                               rst_n,
    input  [DFF_SYNC_INP_BUS_WIDTH-1:0] data_in,
    output [DFF_SYNC_INP_BUS_WIDTH-1:0] data_out
);
    /* packed dimension */                 /* unpacked dimension*/
reg [DFF_SYNC_NUM_FF_STAGES-1:0] dff_chain [DFF_SYNC_INP_BUS_WIDTH-1:0];
// Note: multi-dimensional array can be accessed as shown below
//       reg [7:0] regA [3:0]
//       regA[unpacked_3_thru_0][packed_7_thru_0]
    genvar i;
    generate
        // iterate through unpacked dimension...
        for (i = 0; i < DFF_SYNC_INP_BUS_WIDTH; i = i + 1)
        begin: g_dff_sync
            always @(posedge clk or negedge rst_n)
            begin: p_sync_chain
                if (!rst_n)
                    dff_chain[i] <= {DFF_SYNC_NUM_FF_STAGES{DFF_SYNC_RESET_VALUE}};
                else
                    dff_chain[i] <= {dff_chain[i][DFF_SYNC_NUM_FF_STAGES-1:1],data_in[i]};
            end // p_sync_chain
            assign data_out[i] = dff_chain[i][DFF_SYNC_NUM_FF_STAGES-1];
        end // g_dff_sync
    endgenerate
endmodule // dff_sync

及以下您可以找到将实例化该模块变体的代码，从而导致2xff同步器inset_value = 0，num_ff_stages = 2和inp_bus_width = 1：

 dff_sync #
    (
        .DFF_SYNC_RESET_VALUE ('d0),
        .DFF_SYNC_NUM_FF_STAGES ('d2),
        .DFF_SYNC_INP_BUS_WIDTH ('d1)
    )
    i_dff_sync
    (
        // ---- Inputs ----
        .clk      (clk),
        .rst_n    (rst_n),
        .data_in  (data_in),
        // ---- Outputs ----
        .data_out (data_out)
    ); // i_dff_sync