在 ARM Cortex-A8 上启用 MMU 时出现问题.CPU S5PV210

Question

这些天我只想写一些裸机代码来处理MMU，经过几天的尝试，我仍然无法使其工作。由于我无法使用串行控制台对其进行调试，并且我没有像D-STREAM那样昂贵的调试器，因此我能做的就是在此处粘贴代码并寻求帮助。我不想成为水蛭，但我真的不知道我能提供什么更进一步的信息。

我的 CPU S5PV210基于 cortex-A8 架构我想做的只是做一个平面内存映射，仅表示"虚拟地址==物理地址"之后的代码

 "ldr    pc, =0x30000000n"

只是闪光灯程序。如果注释此行在"enable_mmu">

"orr    r0, r0, #0x0001n"          /* .... .... .... ...1 Enable MMU */

我的闪光灯LED

程序将正常工作，如果我取消注释它，闪光灯LED将停止工作。这是整个程序

#define ttl_base 0x2F000000
#define MMU_DES_FULL_ACESS (3<<10) 
#define MMU_DES_DOMAIN (0<<5) 
#define MMU_DES_EXECUTE_NEVER (0<<4) 
#define MMU_DES_CACHEABLE (1<<3) 
#define MMU_DES_BUFFERABLE (1<<2) 
#define MMU_DES_SECTION (2) 
#define MMU_DES_ATTRIBUTE (MMU_DES_SECTION|MMU_DES_BUFFERABLE|MMU_DES_CACHEABLE|MMU_DES_EXECUTE_NEVER|MMU_DES_DOMAIN|MMU_DES_FULL_ACESS)
void init_mmu()
{
    //Create Translation Table for a flat map (Vitual Address == Physical Address)
    u32 virtualaddr,phyaddr;
    u32 *mmu_tlb_base=(u32 *)ttl_base;
    virtualaddr = 0x0;
    phyaddr = 0x0;
    while(1)
    {
        *(mmu_tlb_base + (virtualaddr>>20)) = (phyaddr & 0xFFF00000) | (MMU_DES_ATTRIBUTE); //map 0x0x30000000-0x30100000 to 0xB0000000-0xB0100000
        virtualaddr+=0x100000;
        phyaddr+=0x100000;
        if (phyaddr==0x00000000)
        {
            break;
        }
    }
}
void enable_mmu()
{
    __asm__(
        "mrc    p15, 0, r0, c1, c0, 0n"
        "bic    r0, r0, #0x3000n"
        "mcr    p15, 0, r0, c1, c0, 0n"    /* Disable Insturection cache */
        "mov    r0, #0n"   
        "mcr    p15, 0, r0, c7, c5, 0n"   /*Instruction cache invalidate all*/
        "mcr    p15, 0, r0, c7, c5, 6n"   /*branch predictor invalidate all*/
        "mcr    p15, 0, r0, c8, c7, 0n"    /* Invalidate data and instruction TLB */
        /*Invalidate entire Data cache*/
        /*Start*/
        "MRC p15, 1, r0, c0, c0, 0n" /* Read Cache Size ID */
        "LDR r3, =0x1ffn"
        "AND r0, r3, r0, LSR #13n" /* r0 = no. of sets - 1 */
        "MOV r1, #0n" /* r1 = way counter way_loop */
        "way_loop:n"
        "MOV r3, #0n" /* r3 = set counter set_loop */
        "set_loop:n"
        "MOV r2, r1, LSL #30n" /* */
        "ORR r2, r3, LSL #5n" /* r2 = set/way cache operation format */
        "MCR p15, 0, r2, c7, c6, 2n" /* Invalidate line described by r2 */
        "ADD r3, r3, #1n" /* Increment set counter */
        "CMP r0, r3n" /* Last set reached yet? */
        "BGT set_loopn" /* if not, iterate set_loop */
        "ADD r1, r1, #1n" /* else, next */
        "CMP r1, #4n" /* Last way reached yet? */
        "BNE way_loopn" /* if not, iterate way_loop */
        /*End*/
        /*Data and Instruction barrier*/
        "dsbn"
        "isbn"

        "mov    r0, #0n"  
        "mcr    p15, 0, r0, c2, c0, 2n" /*Clear L2 Translation Table Entry*/
        "mov    r4, #0x2F000000n"
        "mcr    p15, 0, r4, c2, c0, 0n" /*Write L1 Translation Table Entry*/
        "mvn    r0, #0n"                   
        "mcr    p15, 0, r0, c3, c0, 0n"    /*Write 0xFFFFFFFF to Domain Access Register, which means no permission check*/
        "mrc    p15, 0, r0, c1, c0, 0n"    /* Read SCTLR */  
                                            /* .RVI ..RS B... .CAM */ 
        "bic    r0, r0, #0x3000n"          /* ..11 .... .... .... Clear bit V、bit I */
        "bic    r0, r0, #0x0087n"          /* .... .... 1... .111 Clear bit B/C/A/M */

        "orr    r0, r0, #0x0002n"          /* .... .... .... ..1. Enable Aligment Check */
        "orr    r0, r0, #0x0004n"          /* .... .... .... .1.. Enable Data Caches */
        "orr    r0, r0, #0x1000n"          /* ...1 .... .... .... Enable Instruction Caches */
        "orr    r0, r0, #0x0800n"          /* .... 1... .... .... Enble brach prediction */
        "orr    r0, r0, #0x0001n"          /* .... .... .... ...1 Enable MMU */
        "mcr    p15, 0, r0, c1, c0, 0n"    /* Write back to SCTLR */
        "ldr    sp, =0x3F000000n"
        "ldr    pc, =0x30000000n"
        "loop:n"
        "b loopn"
    );
}

Answer 1

看来你的页表初始化代码是正确的。但是您需要提供MMU_DES_ATTRIBUTE.我认为属性有问题。