如何修复我当前的MIPS 32 SCP寄存器文件的时钟/数据错误

Question

我正在为 Verilog 中的课堂作业构建一个单周期处理器，但我的测试台似乎无法获得正确的输出。我已经正确连接了所有内容，并且它为我的测试台的前半部分生成零，但是一旦我开始输入数据，它就会保持在零。所以我知道我的重置和时钟有效，但在写作部分的某个地方，我忽略了一些东西。我可以使用一双新鲜的眼睛，任何帮助都是值得赞赏的。蒂亚。

注册文件.v：

module registerfile(read1, read2, writeto, writedat, writeenable, out1, out2, clock, reset);
input [4:0] read1;
input [4:0] read2;
input [4:0] writeto;
input [31:0] writedat;
input writeenable, clock, reset;
output [31:0] out1, out2;
// 32 bit registers x 32
reg [31:0] RF[31:0];
reg [31:0] out1;
reg [31:0] out2;
integer i;
always @(posedge reset)
begin
    for (i = 0; i < 32; i++)
        RF[i] <= 0;
    out1 <= 32'h00000000;
    out2 <= 32'h00000000;
end
always @(posedge clock)
begin
    if (writeenable)
        RF[writeto] <= writedat;
    out1 <= RF[read1];
    out2 <= RF[read2];
end
endmodule

RegisterFile_tb.v：

module registerfile_tb ();
reg [4:0] read1;
reg [4:0] read2;
wire [31:0] out1;
wire [31:0] out2;
reg [4:0] writeto;
reg [31:0] writedat;
reg writeenable;
reg clock;
reg reset;
registerfile DUT(read1, read2, writeto, writedat, writeenable, out1, out2, clock, reset);
initial
begin
    clock <= 1;
    reset <= 1;
    #21 reset <= 0;
    #100;
    read1 <= 5'b0;
    read2 <= 5'b0;
    writeto <= 5'b00101;
    writedat <= 32'd0;
    writeenable <= 1;
    #100;
    #21 read1 <= 5'b11010;
    #21 read2 <= 5'b00101;
    #21 read1 <= 5'b00001;
    #21 writedat <= 32'd1; //
    #21 read2 <= 5'b11111;
    #21 read1 <= 5'b01010;
    #21 read2 <= 5'b01110;
end
always @(read1 or read2)
    #21 $display("| read1 = %d | read2 = %d | out1 = %d | out2 = %d |", read1, read2, out1, out2);
endmodule

Answer 1

您的时钟没有切换。您的测试台中应该有一个always #10 clk = !clk;(您可能需要不同的延迟(。

您的显示语句有点奇怪。考虑将其更改为监视器，并将其移动到初始块的顶部附近。

仅供参考。您的代码不会合成。对我来说，可合成的寄存器必须仅由一个始终块分配。您有单独的时钟和复位块。要进行异步重置，请使用以下结构。对于同步复位(大多数FPGA都需要(，则省略or posedge reset

always @(posedge clock or posedge reset)
begin
    if (reset) begin
        for (i = 0; i < 32; i++)
            RF[i] <= 0;
        out1 <= 32'h00000000;
        out2 <= 32'h00000000;
    end
    else begin
        if (writeenable)
            RF[writeto] <= writedat;
        out1 <= RF[read1];
        out2 <= RF[read2];
    end
end