VHDL:如何将二进制数转换为十进制数字

Question

我正在通过一个项目学习VHDL，我想将二进制数转换为十进制数字(也以二进制表示(。我需要这样做，因为我正在以十进制打印数字，如果我尝试不转换它，我会得到十六进制的数字...

例如我有0010 1010 1111 0001(2AF1(，我想要0001 0000 1001 1001 0011(10993(

我必须确保我的二进制数在32位

这一定很简单，因为我在互联网上找不到解决方案...

编辑：此代码正在工作，并将二进制号转换为用二进制(d'10 = b'0001 0000(表示的小数号

    signal val0 : std_logic_vector(31 downto 0);
    signal val1 : std_logic_vector(31 downto 0);
    signal val2 : std_logic_vector(31 downto 0);
    signal val_Mux : std_logic_vector(31 downto 0);
            val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;

    val1(3 downto 0)<= val_MUX(3 downto 0);
    loopA:
        for i in 0 to 6 generate
            val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                    else val_MUX(4*i+7 downto 4*i+4);
            val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                    else val1(4*i+3 downto 4*i); 
    end generate loopA;
    val2(31 downto 28)<= val1(31 downto 28);

    val0 <= (others => '0') when reset='1' else 
        val2 when rising_edge(clk50);

Answer 1

解决方案是在分配一个显示器之前通过2个信号浏览其他信号，并用下面的一个显示分配计数器：

：

signal val0 : std_logic_vector(31 downto 0);
signal val1 : std_logic_vector(31 downto 0);
signal val2 : std_logic_vector(31 downto 0);
signal val_Mux : std_logic_vector(31 downto 0);
        val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;

val1(3 downto 0)<= val_MUX(3 downto 0);
loopA:
    for i in 0 to 6 generate
        val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                else val_MUX(4*i+7 downto 4*i+4);
        val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                else val1(4*i+3 downto 4*i); 
end generate loopA;
val2(31 downto 28)<= val1(31 downto 28);

val0 <= (others => '0') when reset='1' else 
    val2 when rising_edge(clk50);