VHDL 根据下降/rising_edge分配过程中的值

Question

此组件用于检测外部脉冲，并根据特定输入(cs(选择它是否必须依靠rising_edge或falling_edge，但显示下一个问题：

Error (10028): Can't resolve multiple constant drivers for net "contadortemp[7]" at ControlLogic.vhd(46)
Error (10029): Constant driver at ControlLogic.vhd(27)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[6]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[5]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[4]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[3]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[2]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[1]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[0]" at ControlLogic.vhd(46)

问题似乎是将不同的值同名化为contadortemp，但是，我不知道为什么。我应该如何更改contadortemp的辅助逻辑以获得所需的性能？基于两个选项在不同情况下都应该增加相同的信号(contadortemp(，这取决于cs

代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Realiza el conteo y lo reinicia si se llegó al top
entity ControlLogic is
--top: Se activa si se llegó al top (viene de MyTimer)
--clk: Reloj proveido por ClkSelect (pulso externo o prescaler) (viene de MyTimer)
--contador: valor del contador (va a MyTimer)
Port(
cs: in std_logic_vector(2 downto 0);
top: in std_logic;
clk: in std_logic;
contador: out std_logic_vector(7 downto 0)
);
end ControlLogic;
architecture Behavioral of ControlLogic is
signal contadortemp: std_logic_vector (7 downto 0):=(others=>'0');
begin   
falling_proc : process(clk)
begin
if cs = "110" then
if falling_edge(clk) then
if (top='0') then
if contadortemp = "11111111" then
contadortemp    <=  (others=>'0');
else
contadortemp    <=  contadortemp + '1';
end if;
else
contadortemp        <=  (others => '0');
end if;
end if;
else
contadortemp    <= contadortemp;
end if;
end process falling_proc;
rising_proc : process(clk)
begin
if cs /= "110" then
if rising_edge(clk) then
if (top='0') then
if contadortemp = "11111111" then
contadortemp    <=  (others=>'0');
else
contadortemp    <=  contadortemp + '1';
end if;
else
contadortemp        <=  (others => '0');
end if;
end if;
else
contadortemp    <= contadortemp;
end if;
end process rising_proc;
contador <= contadortemp;
end Behavioral;

Answer 1

FPGA 中的寄存器可以使用上升沿或下降沿，但不能同时使用两者。

使用时钟控制块创建一个以当前时钟两倍的速度运行的时钟。然后使用时钟使能来计算奇数或偶数时钟周期。

if rising_edge(fastclock) then
if (cs = "110" and clk = '1') or (cs /= "110" and clk = '0') then
-- counter
end if;
end if;

Answer 2

合并两个进程，因为它们对单个信号敏感(此处为clk(。 尝试在过程中更多地使用变量而不是信号。 毕竟：考虑硬件而不是软件。 尝试这样的事情：

architecture Behavioral of ControlLogic is
--signal contadortemp: std_logic_vector (7 downto 0):=(others=>'0');
begin
falling_and_rising_edge : process(clk)
variable contadorVar    : std_logic_vector(7 downto 0) := "00000000";
begin
if falling_edge(clk) then
if cs = "110" then
if (top='0') then
if contadorVar  = "11111111" then
contadorVar     :=  (others=>'0');
else
contadorVar    :=  contadorVar  + '1';
end if;
else
contadorVar       :=  (others => '0');
end if;
contador    <= contadorVar;
end if;
end if;
if rising_edge(clk) then
if cs /= "110" then
if (top='0') then
if contadorVar  = "11111111" then
contadorVar    :=  (others=>'0');
else
contadorVar    :=  contadorVar  + '1';
end if;
else
contadorVar      :=  (others => '0');
end if;
contador    <= contadorVar; 
end if;
end if;
end process falling_and_rising_edge;
end behavioral;