VHDL测试平台不改变输出ALU 32位

Question

你看，我已经用 modelsim 完成了在 vhdl 上描述 ALU，但是测试平台似乎没有更新解决方案，当我看到仿真时，电路 32 位响应总是说 "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" 我不知道我在测试平台上写错了什么，编译器上还有一个关于电路响应的警告，上面写

着

** 警告：(vsim-8683( 未初始化的输出端口/alu_tb/ALU_test/res(32 下降到 0(没有驱动程序。 此端口将为信号网络贡献价值(

UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU

这是测试平台代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_tb is        
end ALU_tb;
architecture bhv_ALU_tb of ALU_tb is
component ALU
    port(
        a, b: in std_logic_vector(31 downto 0);
        c: in std_logic;
        s: in std_logic_vector(3 downto 0);
        res: out std_logic_vector(32 downto 0));
end component;
signal a, b: std_logic_vector(31 downto 0);
signal c: std_logic;
signal s: std_logic_vector(3 downto 0);
signal re: std_logic_vector(32 downto 0);
begin 
    ALU_test: ALU port map (a => a, b => b, c => c, s => s, res => re);
process begin
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "1111";
    wait for 2 ns;
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "0100";
    wait for 2 ns;
    s <= "0000";
    wait for 2 ns;
    s <= "0001";
    wait for 2 ns;
    s <= "0010";
    wait for 2 ns;
    s <= "0011";
    wait for 2 ns;
    s <= "0100";
    wait for 2 ns;
    s <= "0101";
    wait for 2 ns;
    s <= "0110";
    wait for 2 ns;
    s <= "0111";
    wait for 2 ns;
    s <= "1000";
    wait for 2 ns;
    s <= "1001";
    wait for 2 ns;
    s <= "1010";
    wait for 2 ns;
    s <= "1011";
    wait for 2 ns;
    s <= "1100";
    wait for 2 ns;
    s <= "1101";
    wait for 2 ns;
    s <= "1110";
    wait for 2 ns;
    s <= "1111";
    wait for 2 ns;
end process;
end bhv_ALU_tb;

我知道这个错误似乎是微不足道的"res 未初始化"，但我离开 vhdl 太久了，老实说不知道如何解决它，有什么想法吗？

Answer 1

首先

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

不好..不要使用。您甚至不需要在此文件中使用它们。如果您需要算术，请使用 numeric_std 。

然后：错误出在组件ALU，因为这应该"驱动"res。但是由于您没有发布该代码，因此我们无法为您提供帮助(还(。

附言：目前您不再需要在VHDL中定义组件。你可以写：

ALU_test: entity work.ALU port map