VHDL-如何将1位输出位置连接到几个1位信号

Question

假设我有一个带有输出的门。问题在于我想连接其输出，以便其他几个组件。因此，我需要从此和门中制作许多输出的"副本"，以便我可以将许多组件连接到此输出。您可以使用信号和别名或如何执行此操作？

Answer 1

不，您不需要制作副本 - 其他任何东西都可以"聆听"特定信号。例如：

....
architecture a of entity_name is
  signal and_out : std_logic;
begin
  -- drive the signal we want to use in multiple places, just a normal signal assignment
  and_out <= in1 and in2; 
  -- one block using the signal
  some_block_instance: entity work.some_block
  port map (some_input => and_out,...); 
  -- another block using the signal
  some_other_block_instance: entity work.some_other_block
  port map (some_other_input => and_out,...);
  another_signal <= and_out or in3; -- a signal assignment reading the signal
....

Answer 2

您可能需要找到介绍性的VHDL参考。您可以尝试搜索 vhdl Made forie Easy ，David Pellerin和Douglas Taylor的书。

不，您不需要制作副本。您只需要每个"网"一个唯一的信号。

来自des.vhdl：

DB1: bidir port map (Z => DATA(7),Y => DIN(1), OE => DOE, A => DOUT(1));
DB2: bidir port map (Z => DATA(6),Y => DIN(2), OE => DOE, A => DOUT(2));
DB3: bidir port map (Z => DATA(5),Y => DIN(3), OE => DOE, A => DOUT(3));
DB4: bidir port map (Z => DATA(4),Y => DIN(4), OE => DOE, A => DOUT(4));
DB5: bidir port map (Z => DATA(3),Y => DIN(5), OE => DOE, A => DOUT(5));
DB6: bidir port map (Z => DATA(2),Y => DIN(6), OE => DOE, A => DOUT(6));
DB7: bidir port map (Z => DATA(1),Y => DIN(7), OE => DOE, A => DOUT(7));
DB8: bidir port map (Z => DATA(0),Y => DIN(8), OE => DOE, A => DOUT(8));
DO_EN:  invbuf port map ( A => DOE_N, Z => DOE);

组件声明：

package des_pack is

    component bidir
        port (
            Z:      inout   std_logic;
            Y:      out std_logic;
            OE:     in  std_logic;
            A:      in  std_logic
        );
    end component;
...
    component invbuf
        port (
            A:      in  std_logic;
            Z:      out std_logic
        );

信号doe声明：

architecture behave of des is
...
    signal DOE:                 std_logic;
...
begin

这是来自DES的VHDL实现的GPLV3。https://dl.dropboxusercontent.com/u/25980826/vhdl_des.tar.gz

Answer 3

您说要将一个和门输出连接到许多其他组件。要pedantic，您实际上会将其连接到这些组件上的端口：我们可以假设所有这些端口都是输入端口吗？如果是这样...

创建一个简单的信号，然后将其连接到输出端口和所有输入端口。马丁用细节击败了我...