VHDL 计数器 1 错误

Question

我已经完成了代码，它可以工作，但是，当我尝试编写测试台时，我遇到了一些麻烦。输入 x 设置为 8 位，x： IN 设置为 BIT_VECTOR（N -1 降至 0）。当我编写测试台时，我不输入位号。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY Count_ones IS
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N);
END ENTITY ;
architecture Behavioral of Count_ones is
    TYPE count is Array (N DOWNTO 1) OF Natural;
    signal a : count;
begin
  a(0) <= 1 when (x(0) = '1')
  else
       0;
  gen: FOR i IN N-1 DOWNTO 0
  GENERATE
            a(i+1) <= (a(i)+1) when (x(i)='0')
            else
                  a(i);
END GENERATE;
y <= a(N-1);
end Behavioral;

试验台：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY Count_ones_TB IS
END Count_ones_TB;
ARCHITECTURE behavior OF Count_ones_TB IS 

COMPONENT Count_ones
PORT(
     x : IN  std_logic_vector(7 downto 0);
     y : OUT  std_logic_vector(0 to 3)
    );
 END COMPONENT;
--Inputs
signal x : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal y : std_logic_vector(0 to 3);

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Count_ones PORT MAP (
      x => x,
      y => y
    );
stim_proc: process
begin       
        x <= "00010101";
        wait for 100 ns;    
        x <= "00001001";
        wait for 100 ns;
        x <= "11111111101"
        wait for 100ns;
  -- insert stimulus here 
  wait;
end process;
END;

错误是

实体端口 x 与组件端口的类型 std_logic_vector 不匹配实体端口 y 与组件端口的类型 std_logic_vector 不匹配

请帮助我，我真的找不到解决这个问题的方法。

Answer 1

特定问题的答案是实体中的端口类型、组件中的端口和信号类型必须匹配。这是指向包含这些错误的代码的链接，并更正了更多错误。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY Count_ones IS
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N);
END ENTITY ;
architecture Behavioral of Count_ones is
    TYPE count is Array (N DOWNTO 0) OF Natural;
    signal a : count;
begin
  a(0) <= 1 when (x(0) = '1')
  else
       0;
  gen: FOR i IN N-1 DOWNTO 0
  GENERATE
            a(i+1) <= (a(i)+1) when (x(i)='0')
            else
                  a(i);
END GENERATE;
y <= a(N-1);
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY Count_ones_TB IS
END Count_ones_TB;
ARCHITECTURE behavior OF Count_ones_TB IS 

COMPONENT Count_ones
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); 
          y: OUT NATURAL RANGE 0 TO N); 
END COMPONENT;
--Inputs
signal x : BIT_VECTOR(7 downto 0) := (others => '0');
--Outputs
signal y : natural;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Count_ones PORT MAP (
      x => x,
      y => y
    );
stim_proc: process
begin       
        x <= "00010101";
        wait for 100 ns;    
        x <= "00001001";
        wait for 100 ns;
        x <= "11111101";
        wait for 100ns;
  -- insert stimulus here 
  wait;
end process;
END;

但是，我必须指出，您距离实现尝试计算数量的目标还有很长的路要走。

正因为如此：

1. 我对你的代码的更正并不是唯一的正确答案。在事实上，我的更正甚至不是一个好的答案。我只是做了使代码编译和运行的最小更正。你需要要非常仔细地考虑您的所有端口和信号的类型设计应该是。
2. 我的更正不会使您的代码正常工作，即计算数量 的。