所有分配中的Verilog错误

Question

verilog错误

我正在尝试学习Verilog。此代码是针对使用计数器的七个段LED制作的。但是我无法为NR分配值，它会产生错误。我制作了一台状态机，希望在每个正时钟之后在七个段中获得下一个数字。

module LED ( nr,clk);
     input  clk;
     output [6:0]nr; //output led seven bit number
     reg [6:0]nr;
     reg [2:0]state;

    always @(posedge clk);
       begin
          state <= 3'b000; // assigning at each clock
          case (state)
          3'b000:
            begin
            nr <= 7'b0000001;  
            state <= 3'b001;
           end
          3'b001:
            begin
            nr <= 7'b0011111;
            state <= 3'b010;
            end
          3'b010:
            begin
            nr <= 7'b0100101;
            state <= 3'b011;
            end
          3'b011:
           begin
           nr <= 7'b0001100;
           state <= 3'b100;
           end
         3'b100:
          begin
          nr <= 7'b1011010;
          state <= 3'b101;
          end
         3'b101:
          begin
          nr <= 7'b1001000;
          state <= 3'b110;
          end
         3'b110:
          begin
          nr <= 7'b1000000;
          state <= 3'b111;
          end
         3'b111:
          begin
          nr <= 7'b0011101;
          state <= 3'b000;
          end
     end
    endmodule

Answer 1

always @(posedge clk) no semicolon！