这是加法器的外观吗?以及如何对其进行基准测试

Question

我试图使两者兼具和前面的N-Bits Adder外观，当我做N-Bits全加法器时，我决定将其重复使用以使其重复使用，但是只是对我来说并不正确。

完整加法器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
    Port ( 
        FA_A    : in  STD_LOGIC;
        FA_B    : in  STD_LOGIC;
        FA_Cin  : in  STD_LOGIC;
        FA_S    : out STD_LOGIC;
        FA_Cout : out STD_LOGIC
    );
end FullAdder;
architecture Behavior of FullAdder is 
begin
    FA_S    <= FA_A XOR FA_B XOR FA_Cin ;
    FA_Cout <= (FA_A AND FA_B) OR (FA_Cin AND FA_A) OR (FA_Cin AND FA_B);
end Behavior;

n位块：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdderNBits is
    Generic( N : integer  := 8 );
    Port ( 
        A    : in  STD_LOGIC_VECTOR(0 to N-1);
        B    : in  STD_LOGIC_VECTOR(0 to N-1);
        Cin  : in  STD_LOGIC;
        S    : out STD_LOGIC_VECTOR(0 to N-1);
        Cout : out STD_LOGIC
    );
end FullAdderNBits;
architecture Behavior of FullAdderNBits is
    signal temp_B     : STD_LOGIC_VECTOR(0 to N-1);
    signal carries    : STD_LOGIC_VECTOR(0 to N);
    component FullAdder Port(
            FA_A    : in  STD_LOGIC;
            FA_B    : in  STD_LOGIC;
            FA_Cin  : in  STD_LOGIC;
            FA_S    : out STD_LOGIC;
            FA_Cout : out STD_LOGIC
        );
    end component;
begin
    temp_B <= not B when Cin = '1' else B;
    carries(N) <= Cin;
    ForGenerate: for i in (N-1) downto 0 generate
        UX: FullAdder port map(
            A(i),
            temp_B(i),
            carries(i+1),
            S(i),
            carries(i)
        );
    end generate ForGenerate;
    Cout <= carries(0);
end Behavior;

向前看：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LookAheadAdder is
    Port ( 
        LAA_A    : in  STD_LOGIC;
        LAA_B    : in  STD_LOGIC;
        LAA_Cin  : in  STD_LOGIC;
        LAA_S    : out STD_LOGIC;
        LAA_Cout : out STD_LOGIC
    );
end LookAheadAdder;
architecture Behavior of LookAheadAdder is 
    signal P : STD_LOGIC;
    signal G : STD_LOGIC;
begin
    P       <= LAA_A xor LAA_B;
    G       <= LAA_A and LAA_B;
    LAA_S    <= P    xor LAA_Cin;
    LAA_Cout <= G or (P and LAA_Cin);
end Behavior;

相同的n位块，刚刚更改了组件：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LookAheadNBitsAdder is
    Generic( N : integer  := 8 );
    Port ( 
        A    : in  STD_LOGIC_VECTOR(0 to N-1);
        B    : in  STD_LOGIC_VECTOR(0 to N-1);
        Cin  : in  STD_LOGIC;
        S    : out STD_LOGIC_VECTOR(0 to N-1);
        Cout : out STD_LOGIC
    );
end LookAheadNBitsAdder;
architecture Behavior of LookAheadNBitsAdder is
    signal temp_B     : STD_LOGIC_VECTOR(0 to N-1);
    signal carries    : STD_LOGIC_VECTOR(0 to N);
    component LookAheadAdder Port(
            LAA_A    : in  STD_LOGIC;
            LAA_B    : in  STD_LOGIC;
            LAA_Cin  : in  STD_LOGIC;
            LAA_S    : out STD_LOGIC;
            LAA_Cout : out STD_LOGIC
        );
    end component;
begin
    temp_B <= not B when Cin = '1' else B;
    carries(N) <= Cin;
    ForGenerate: for i in (N-1) downto 0 generate
        UX: LookAheadAdder port map(
            A(i),
            temp_B(i),
            carries(i+1),
            S(i),
            carries(i)
        );
    end generate ForGenerate;
    Cout <= carries(0);
end Behavior;

如何使用一个测试更快？我没有FPGA，所以我可以使用Modelsim做到这一点吗？我尝试了模拟，但看起来繁殖并没有任何延迟，波浪只是从一个状态跳到另一个状态。

Answer 1

这两个都写为组合逻辑。意味着输入将立即传播到输出。查看哪个"更快"的唯一方法是引入时钟并开始计数时钟周期。您可以看到哪种将在芯片上使用较少的资源，但是如果它们都以组合逻辑(不是顺序(编写的，那么在模拟中将立即输出。