我该如何在VHDL中的时钟中暂停2Hz

Question

我在vhdl中是新的，我需要在counter Project中暂停2Hz或VHDL程序中的0.5Hz。

另一方面，我有以下代码：

architecture behavior of Counter is
signal q: std_logic_vector(7 downto 0);
begin
process(clock, choose)
  begin
    if clear = '1' then
        q <= q - q;
    else
        if rising_edge(clock) then
            -- when choose is '1', the process if for increment
            if(choose = '1') then
                case incodec is           
                    when "001" => q <= q + 1;
                    when "011" => q <= q + 10;
                    when "111" => q <= q + 11;
                    when others => q <= q;
                end case;
            -- when choose is '0', the process if for decrement
            elsif choose = '0' then
                case incodec is           
                    when "001" => q <= q - 1;
                    when "011" => q <= q - 10;
                    when "111" => q <= q - 11;
                    when others => q <= q;
                end case;
            end if;
        end if;
    end if;
    case q(7 downto 4) is
                                  --  6543210
        when "0000" => hex7 <= "1000000"; --0
        when "0001" => hex7 <= "1111001"; --1
        when "0010" => hex7 <= "0100100"; --2
        when "0011" => hex7 <= "0110000"; --3
        when "0100" => hex7 <= "0011001"; --4
        when "0101" => hex7 <= "0010010"; --5
        when "0110" => hex7 <= "0000010"; --6
        when "0111" => hex7 <= "1111000"; --7
        when "1000" => hex7 <= "0000000"; --8
        when "1001" => hex7 <= "0010000"; --9
        when "1010" => hex7 <= "0001000"; --10/A
        when "1011" => hex7 <= "0000011"; --11/B/b
        when "1100" => hex7 <= "1000110"; --12/C
        when "1101" => hex7 <= "0100001"; --13/D/d
        when "1110" => hex7 <= "0000110"; --14/E
        when "1111" => hex7 <= "0001110"; --15/F
        when others => hex7 <= "0111111"; -- -
    end case;
    case q(3 downto 0) is
                                  --  6543210
        when "0000" => hex6 <= "1000000"; --0
        when "0001" => hex6 <= "1111001"; --1
        when "0010" => hex6 <= "0100100"; --2
        when "0011" => hex6 <= "0110000"; --3
        when "0100" => hex6 <= "0011001"; --4
        when "0101" => hex6 <= "0010010"; --5
        when "0110" => hex6 <= "0000010"; --6
        when "0111" => hex6 <= "1111000"; --7
        when "1000" => hex6 <= "0000000"; --8
        when "1001" => hex6 <= "0010000"; --9
        when "1010" => hex6 <= "0001000"; --10/A
        when "1011" => hex6 <= "0000011"; --11/B/b
        when "1100" => hex6 <= "1000110"; --12/C
        when "1101" => hex6 <= "0100001"; --13/D/d
        when "1110" => hex6 <= "0000110"; --14/E
        when "1111" => hex6 <= "0001110"; --15/F
        when others => hex6 <= "0111111"; -- -
    end case;
end behavior

当程序编译显示以下错误时：

错误（10818）：在Counter.VHD（28）上不能推断" Q [0]"登记 我不知道什么是

请帮助我:(

Answer 1

您的代码包含多个错误：

• 不要使用Synopsys软件包进行算术操作。
  使用软件包numeric_std和类型signed和/或unsigned代替。
• q表示状态，并将合成为触发器。
  因此，在FPGA技术上，初始化它们：:= (others => '0')
• clear是一个异步信号，因此在灵敏度列表中列出。
• choose是一个同步信号，所以不要在灵敏度列表中列出它。
• 当您要添加数字1,2,3时，然后使用适当的整数文字或将文字明确指定为二进制。默认值是十进制。
• 使用变量将通过消除重复来缩短代码。
• 清除q应通过分配所有零以汇总： (others => '0')。
来完成。
• a循环和另一个变量可以进一步减少您的代码并删除重复的代码的另一个大部分。
• 用户变量hex还将删除一个额外的寄存器阶段，这很可能是大多数设计师打算的。
• 您评论了7段显示6543210的段名，但通常命名为GFEDCBA。
• 您应该将7段解码器放入单独的实体或功能以提高重复性。
• 您的7段显示代码低活动，但设计师应编写高活动代码。低活动是由于董事会或展示设计所致，而不是解码器的责任。将hex分配给hex7。
时可以进行反转。

这是改进的代码：

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.numeric_std.all;

entity Counter is
    -- ...
end entity;

architecture behavior of Counter is
    signal q : unsigned(7 downto 0) := (others => '0');
begin
    process(clock, clear)
        variable decoded : positive;
        variable hex     : std_logic_vector(13 downto 0);
    begin
        case incodec is           
            when "001" =>  decoded := 1;
            when "011" =>  decoded := 2;
            when "111" =>  decoded := 3;
            when others => decoded := 0;
        end case;
        if clear = '1' then
            q <= (others => '0');
        elsif rising_edge(clock) then
            if(choose = '1') then     -- when choose is '1', the process if for increment
                q <= q + decoded;
            elsif (choose = '0') then -- when choose is '0', the process if for decrement
                q <= q - decoded;
            end if;
        end if;
        for i in 0 to 1 loop
            case q(i*4+7 downto i*4) is            --  6543210
                when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0
                when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1
                when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2
                when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3
                when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4
                when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5
                when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6
                when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7
                when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8
                when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9
                when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A
                when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b
                when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C
                when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d
                when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E
                when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F
                when others => hex(i*7+6 downto i*7) := "0111111"; -- -
            end case;
        end loop;
        hex7 <= hex(13 downto 7);
        hex6 <= hex(6 downto 0);
    end process;
end architecture;