案例语句中接近"<="的 Verilog 语法错误

Question

在这段代码中：

reg [4:0] status_led = 5'b00100;
case (status_led)
default: begin                   
if (rotation) begin
status_led[4] <= status_led[3];
status_led[3] <= status_led[2];
status_led[2] <= status_led[1];
status_led[1] <= status_led[0];
status_led[0] <= status_led[4];
end else if (~rotation) begin
status_led[4] <= status_led[0];
status_led[3] <= status_led[4];
status_led[2] <= status_led[3];
status_led[1] <= status_led[2];
status_led[0] <= status_led[1];
end
end
endcase

我收到错误"<=附近的语法错误"。为什么这是一个错误？

Answer 1

您没有始终在内部定义您的案例，因此出现错误。这应该可以解决您的问题。一个好主意是不要将组合和顺序总是块混合在一起。

reg [4:0] status_led = 5'b00100;
always@(posedge clk) begin
case (status_led)
default: begin                   
if (rotation) begin
status_led[4] <= status_led[3];
status_led[3] <= status_led[2];
status_led[2] <= status_led[1];
status_led[1] <= status_led[0];
status_led[0] <= status_led[4];
end else if (~rotation) begin
status_led[4] <= status_led[0];
status_led[3] <= status_led[4];
status_led[2] <= status_led[3];
status_led[1] <= status_led[2];
status_led[0] <= status_led[1];
end
end
endcase
end