除了 Verilog 建模之外，有没有办法为零延迟/宽度故障编写断言或检查器?

Question

我正在验证时钟本身，想知道是否有办法标记零宽度故障？

Answer 1

这应该有效。

property check_for_glitch_fall(clk, bit disable_chk);
  realtime fall_time;
  disable iff(disable_chk)
   @(posedge clk)
     (1, fall_time = $realtime) |=>
   @(negedge clk)
     (($realtime - fall_time) != 0);  
endproperty : check_for_glitch_fall

Answer 2

initial begin 
    #100 
    a=0; 
    b=0; 
    #10 
    a=1;
    b=1;
    #100
    forever 
        #10 a = ~a; 
end
initial begin
    #500
    $finish;
end
always @(a) begin 
    $display("%f edge on a %d", $realtime, a); 
    b=1; 
    b=0; 
end
always @(b) begin 
    $display("%f edge on b %d", $realtime, b); 
    a=0; 
    a=1; 
end