系统Verilog错误："already exists; must not be redefined as a named block"

Question

我正在创建一个具有隐式数据路径的状态机，并收到三个我无法解决的错误。

对于结尾情况错误，我已经确保所有开头在 always 块中都有相应的结尾。

对于完成错误，状态只定义过一次，所以我不确定。

对于 ; 错误，我不知道为什么它不希望我包含 countx 和 county 语句。

任何帮助将不胜感激！

module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour,
input logic start, output logic done,
output logic [7:0] vga_x, output logic [6:0] vga_y,
output logic [2:0] vga_colour, output logic vga_plot);
enum logic [1:0] {Load = 2'b00, Increment = 2'b01, Out = 2'b10, Finish = 2'b11} state, next_state;
logic [7:0] countx, county;

always @ (posedge clk) begin
case(state)
Load:
if(rst_n == 0) 
next_state <= Load; 
else if (start == 1) 
next_state <= Increment;
else begin
next_state <= Load; end
//initialize counter
countx <= 0;    
county <= 0;
Increment: 
if(rst_n == 0) 
next_state <= Load;
else if (county < 119 && countx < 159) begin
county <= county+1; 
next_state <= Increment; end                
else if (countx < 159) begin
countx <= countx +1;
next_state <= Increment; end
else 
next_state <= Finish;
//output            
vga_y <= county;
vga_x <= countx;
vga_colour <= countx % 8;           
vga_plot <= 1;
Finish: 
done <= 1;          
if(rst_n == 0) 
next_state <= Load; 
else begin
next_state = Finish; end
Default: 
vga_y <= county;
vga_x <= countx;
done <= 0;
vga_plot <= 0;
endcase
end
endmodule

以下是我遇到的错误：

** Error: fillscreen.sv(22): near ";": syntax error, unexpected ';', expecting ':'
** Error: fillscreen.sv(54): near "endcase": syntax error, unexpected endcase
** Error: fillscreen.sv(25): 'Increment' already exists; must not be redefined as a named block
** Error fillscreen.sv(43): 'Finish' already exists; must not be redefined as a named block

Answer 1

对于任何情况，如果该情况的代码块有多行，您都需要包含begin..end，就像 if 语句或总是块一样(请参阅内联注释，不仅仅是缺少begin..end)：

case(state) // <- Note, you never assign state, only next_state, might want to review your code for correctness
Load: begin // <- This case has multiple lines
if (rst_n == 0) begin // <- I do begin..end for EVERYTHING as I inevitably come back and add lines in the body which can lead to bugs if there is no begin..end, like {..} in C
next_state <= Load;
end
else if (start == 1) begin
next_state <= Increment;
end
else begin
next_state <= Load;
end
//initialize counter
countx <= 0;    
county <= 0;
end
Increment: begin
if (rst_n == 0) begin
next_state <= Load;
end
else if (county < 119 && countx < 159) begin
county <= county+1; 
next_state <= Increment;
end                
else if (countx < 159) begin
countx <= countx +1;
next_state <= Increment;
end
else begin
next_state <= Finish;
end
//output            
vga_y <= county;
vga_x <= countx;
vga_colour <= countx % 8;           
vga_plot <= 1;
end
Finish: begin
done <= 1;          
if (rst_n == 0) begin
next_state <= Load; 
end
else begin
next_state <= Finish; // Should be non-blocking
end
end
default: begin // <- Should be lower-case "default"
vga_y <= county;
vga_x <= countx;
done <= 0;
vga_plot <= 0;
end
endcase