在绑定模块实例化中,我可以使用来自顶部模块的连线作为输入吗?(SystemVerilog)



我有一个简单的模块PRINTER,我想通过绑定到一个测试台BIG_TB中的另一个模块BIG_DUT来实例化它。BIG_DUT有另一个模块SMALL_DUT的实例,它包含了我想在PRINTER中使用的大部分内容。我有另一个测试台SMALL_TB,它有一个SMALL_DUT的实例和一个PRINTER的实例,在这个测试台中,我想将PRINTER绑定到SMALL_DUT。

在我的PRINTER模块中,我需要一根存在于任一测试台以及BIG_DUT中的导线,但不存在于SMALL_DUT中。是否有任何方法可以使用测试台上的导线,而不是试图访问BIG_DUT/SMALL_DUT内部的导线,同时仍然可以轻松访问SMALL_DUT中的其他导线/材料?

示例代码:

module SMALL_DUT();
// Stuff I want to use in the PRINTER
...
endmodule

module BIG_DUT(
input wire big_dut_input
);
SMALL_DUT small_dut_in_big();
endmodule

module PRINTER(
// Can I take input here from tb?
);
// For BIG_TB, I could use big_dut_input and small_dut_in_big.stuff_i_want_to_use
// For SMALL_TB, there is no wire I could use, but I can reference stuff_i_want_to_use
endmodule

module BIG_TB();
wire my_tb_wire_big;  // Want to use this in PRINTER, also present in BIG_DUT
BIG_DUT big_dut(
.big_dut_input(my_tb_wire_big)
);
// I could potentially do
// bind big_dut.small_dut_in_big
// here to get the same access pattern to stuff inside PRINTER
bind big_dut
PRINTER big_printer(
// Could I input my_tb_wire_big here?
);
endmodule

module SMALL_TB();
wire my_tb_wire_small;  // Same usage as my_tb_wire_big in PRINTER
...
SMALL_DUT small_dut();
bind small_dut
PRINTER small_printer(
// Could I input my_tb_wire_small here?
);
endmodule

(在这个简单的例子中,我当然可以向SMALL_DUT添加另一个输入,但这在我的真实代码中使用,我不希望那里有额外的输入。(

您可以始终在实例端口连接中放置分层引用。无论是否使用bind构造,这都是正确的。

module SMALL_DUT();
bit stuff;
...
endmodule
module BIG_DUT(
input wire big_dut_input
);
SMALL_DUT small_dut_in_big();
endmodule
module PRINTER(
input signal1, signal2, signal3)
// stuff
endmodule

module BIG_TB();
wire my_tb_wire_big;  // Want to use this in PRINTER, also present in BIG_DUT
BIG_DUT big_dut(
.big_dut_input(my_tb_wire_big)
);
bind big_dut
PRINTER big_printer(
BIG_TB.my_tb_wire_big, small_dut_in_big.stuff);
);
endmodule

module SMALL_TB();
wire my_tb_wire_small;  // Same usage as my_tb_wire_big in PRINTER
...
SMALL_DUT small_dut();
bind small_dut
PRINTER small_printer(
SMALL_TB.my_tb_wire_small, stuff
);
endmodule

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