System Verilog中全加法器的测试台

Question

`timescale 1ns/10ps
module testbench_lab3 ();
logic [2:0] a, b, s;
logic c_out;
logic [3:0] c;
rc_adder4 UUT (

);
initial begin
a = 0;
forever begin
#10 a++;
end
end
// COMPLETE BY WRITING AN INITIAL BLOCK FOR b. 
// Set initial value for b equal to 0 and increment b every 20 time units


initial begin
$display("TIME | A B | S CO");   
$display("-----------------");    
$monitor("  %2d | %d %d | %d %b", 
$time, a, b, s, co);         
#160;
$finish();
end
endmodule

/////////////////////////////////////////////////这是我的加法器模块:

module rc_adder_slice (
input logic a, b, c_in,
output logic s,c_out
);
logic p, g;
assign p = a ^ b;
assign g = a & b;
assign s = p ^c_in;
assign c_out = (p & c_in)| g;
endmodule

\\\\\\\\\\\\\\\\\
这是我multi-bit加法器模块:

module rc_adder4 (
input logic[2:0]a, b,
output logic[2:0] s, 
output logic c_out
);
logic [3:0] c;
rc_adder_slice UUT[2:0] (
.a(a),
.b(b),
.c_in(c[2:0]),
.s(s),
.c_out(c[3:1])
);

// COMPLETE USING ARRAY INSTANCING


assign c[0] = 1'b0;// COMPLETE
assign c_out = c[3];// COMPLETE

endmodule

我不知道怎么写测试台。我只有rc_adder4 ut ()(; 和//完成为b写一个初始块。//设置b的初始值为0，然后每隔20个时间单位增加b。有人能帮帮我吗?

Answer 1

您没有将任何端口连接到您的UUT。将rc_adder4 UUT ( );更改为rc_adder4 UUT ( .a(a), .b(b), .s(s), .c_out(c_out) );

也:

• b需要在您的测试台中分配
• 有一个co应该是c_out
• c在你的测试台没有被使用

Answer 2

对你的代码做了一些修改。

`timescale 1ns/10ps
module testbench_lab3 ();
logic [2:0] a, b, s;
logic c_out;
logic [3:0] c;
rc_adder_slice UUT[2:0] (
.a(a),
.b(b),
.c_in(c[2:0]),
.s(s),
.c_out(c[3:1])
);
initial begin
a = 0;
b = 0;
c = 0;
forever begin
// #10 a=$urandom; b=$urandom; c=$urandom; //Uncomment if want to use random values
#10 ++a; ++b; ++c;
end
end
// COMPLETE BY WRITING AN INITIAL BLOCK FOR b. 
// Set initial value for b equal to 0 and increment b every 20 time units
initial begin
$display("TIME | A B | S CO");   
$display("-----------------");    
$monitor("  %2d | %d %d | %d %b", 
$time, a, b, s, c_out);         
#160;
$finish();
end
endmodule