在System Verilog中,我有多个状态,其中一些状态被使用了两次,我怎么知道这是我第一次通过这个状态还是第二次?
例如,如果这是我第二次想要结束进程并重新开始。如果是第一次,再做一次。
任何想法都有帮助
如果您只需要执行某些状态两次,请将它们设置为两个不同的状态。您可以将公共逻辑部分放在函数中。
always_ff @(posedge clk or posedge reset)
if (reset) state <= IDLE else
case (STATE)
IDLE: if (start) STATE <= ST1;
ST1: begin STATE <= ST2; fST(); end
ST2: begin STATE <= IDLE; fST(); end
default: STATE <= IDLE;
endcase
function void fST;
// stuff that needs to be done
end function
如果需要两次以上,可以放入计数器
always_ff @(posedge clk or posedge reset)
if (reset) STATE <= IDLE else
case (STATE)
IDLE: if (start) begin STATE <= ST; counter <=0; end
ST: begin
if (counter > N) STATE <= IDLE;
counter <= counter + 1;
// stuff that needs to be done
end
default: STATE <= IDLE;
endcase
如果你把你的FSM分为always_comb
和always_ff
,你将需要一个下一个状态和下一个计数器变量。
always_ff @(posedge clk or posedge reset)
if (reset) STATE <= IDLE else
begin
STATE <= NXSTATE;
COUNTER <= NXCOUNTER;
end
always_comb
case (STATE)
IDLE: if (start) begin NXSTATE = ST; COUNTER <=0; end
ST: begin
if (COUNTER > N) NXSTATE = IDLE;
NXCOUNTER = NXCOUNTER + 1;
// stuff that needs to be done
end
default: NXSTATE = IDLE;
endcase