VHDL -使用一个实体的输出作为另一个实体的输入

Question

我正在尝试使用超声波传感器制作基本距离指示模块。当我将相同的代码转储到我的FPGA板(IIT-B开发的Helium V1.1)时，由于时钟频率太高，板中的所有led都开始发光。所以现在我正在使用分频器来降低我的时钟速度，但我不知道如何使用我的分频器代码的输出作为输入到我的主代码。有人可以帮助我，因为这是我第一次在FPGA上工作，我还不太了解VHDL吗?

分频器代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture bhv of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
begin
process(clk,reset)
begin
if(reset='1') then
count<=1;
tmp<='0';
elsif(clk'event and clk='1') then
count <=count+1;
if (count = 25000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end bhv; 

使用超声波测量距离的代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ultrasonic is
    port(
    CLOCK: in std_logic;
    LED: out std_logic_vector(7 downto 0);
    TRIG: out std_logic;
    ECHO: in std_logic
    );
end ultrasonic;
architecture rtl of ultrasonic is
signal microseconds: std_logic;
signal counter: std_logic_vector(17 downto 0);
signal leds: std_logic_vector(7 downto 0);
signal trigger: std_logic;
begin
    
    process(CLOCK)
    variable count0: integer range 0 to 7;
    begin
        if rising_edge(CLOCK) then
            if count0 = 5 then
                count0 := 0;
            else
                count0 := count0 + 1;
            end if;
            if count0 = 0 then
                microseconds <= not microseconds;
            end if;
        end if;
    end process;
    
    process(microseconds)
    variable count1: integer range 0 to 262143;
    begin
        if rising_edge(microseconds) then
            if count1 = 0 then
                counter <= "000000000000000000";
                trigger <= '1';
            elsif count1 = 10 then
                trigger <= '0';
            end if;
            if ECHO = '1' then
                counter <= counter + 1;
            end if;
            if count1 = 249999 then
                count1 := 0;
            else
                count1 := count1 + 1;
            end if;
        end if;
    end process;
    
    process(ECHO)
    begin
        if falling_edge(ECHO) then
            if counter < 291 then
                leds <= "11111111";
            elsif counter < 581 then
                leds <= "11111110";
            elsif counter < 871 then
                leds <= "11111100";
            elsif counter < 1161 then
                leds <= "11111000";
            elsif counter < 1451 then
                leds <= "11110000";
            elsif counter < 1741 then
                leds <= "11100000";
            elsif counter < 2031 then
                leds <= "11000000";
            elsif counter < 2321 then
                leds <= "10000000";
            else
                leds <= "00000000";
            end if;
        end if;
    end process;
    
    LED <= leds;
    TRIG <= trigger;
    
end rtl;

我正在使用Quartus来模拟这些代码。

Answer 1

欢迎学习HDL语言:)

对于模拟，clock_out在灵敏度列表中缺失process(...)

对于合成/实现，您可能需要检查所有进程，因为它们应该依赖于时钟信号。我了解到在时钟信号以外的其他信号上使用上升/下降沿被认为是不好的做法。

你可能想要一个像这样的模式:

... 
-- entity declaration
    s : in std_logic;
... 
-- architecture declaration
    signal s_d : std_logic;
begin
...
process(clk)
begin
    if rising_edge(clk) then
        -- s_d is s one clock cycle delayed
        s_d <= s;
        -- detect s transition from 0 to 1 == rising edge
        if s = '1' and s_d = '0' then
            -- Code dependent on rising edge s
        end if;
    end if;
end process;

注:s可能是内部信号，不需要来自实体。如果s是一个频闪(用相同的时钟长1个时钟周期)，则不需要s_d，因为不需要检测边缘，只需要检测信号状态。