带有d_flip - flop的计数器笑脸

Question

我正试图用VHDL编写笑脸计数器的代码，带有触发器但是我得到了一些关于width mismatch的错误;我不知道到底是哪里出了问题。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Smiley_Faces is
Port ( Clk, Reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Smiley_Faces;
architecture Behavioral of Smiley_Faces is
signal NS, PS:std_logic_vector(5 downto 0):= (others => '0');
begin
--- Memory Component
D_ff:process(reset,clk)
begin
if(reset='1') then
ps <= "0000";
elsif(rising_edge(clk)) then
ps<=nS;
end if;
end process;
-- Combination Logic
NS <= "010000" when ps="000000" else
"000110" when ps="010000" else
"010110" when ps="000110" else
"001111" when ps="010110" else
"011111" when ps="001111" else
"101111" when ps="011111" else
"111111" when ps="101111" else
"000000" when ps="111111" else
"000000";
Q <= PS;

end Behavioral;

附上笑脸状态机的图片

Answer 1

多件事

1. 您将PS设置为6位宽，但您的重置语句仅分配4位

   if(reset='1') then
   ps <= "0000";`
   

2. 你用PS的值赋值Q，但它们不是相同的位宽度。要么你需要将Q更新为6位，要么将代码编辑为:

   Q <= PS(3 downto 0);