VHDL相当于Verilog $setup

Question

我需要一个VHDL实体/体系结构，它与下面使用$setup关键字检查输入时间的Verilog模块完全相同。是否有一种方法可以在不使用混合VHDL- verilog模拟的情况下在VHDL本地做到这一点?

`timescale 1ns/10ps
module sim_check_setup_posedge(
input wire data_event,
input wire ref_event
);
reg notifier;
specify
specparam tSU = 1;    // 1 ns
$setup(data_event, posedge ref_event, tSU, notifier);
endspecify
endmodule

以下是我迄今为止对VHDL代码的描述:

library ieee;
use ieee.std_logic_1164.all;
entity sim_check_setup_posedge is
port(
data_event :in std_logic;
ref_event  :in std_logic
);
end entity;
architecture beh of sim_check_setup_posedge is
begin
-- ?? how to implement $setup here?
end architecuture;

Answer 1

您可以使用预定义属性(这里的last_event)和根据示例的检查器实体或根据注释的过程的组合轻松地在VHDL中实现模拟的基本定时检查。下面是一个设置时间检查器的示例:

library ieee;
use ieee.std_logic_1164.all;
entity SetupCheckEntity is
generic (
tSU : time
);
port (
data_event :in std_logic;
ref_event  :in std_logic
);
end entity;
architecture a of SetupCheckEntity is
begin
SetupCheck : process (ref_event)
begin
if (rising_edge(ref_event)) then
-- Warn if setup time not met or data not valid ('X'/'U')
if (data_event'last_event < tSU or data_event = 'X' or data_event = 'U') then
report "SetupCheckEntity: Setup failure, expected " & time'image(tSU) & ", got " & time'image(data_event'last_event) & "." severity warning;
end if;
end if;
end process;
end a;

你可以很容易地修改它来检查相对于一个或两个ref_event边(可能依赖于另一个泛型)，或者扩展它来检查保持时间。我让设置时间是一个通用的，但你可以很容易地使用常数。你也可以在这个实体中调用下面的过程来代替process。

大致相同的代码可以放在一个过程中，如下面的测试台中所示，该测试台中显示了给出相同基本结果的实体和过程方法。

library ieee;
use ieee.std_logic_1164.all;
entity test is
end;
architecture a of test is
constant tCK : time := 20 ns;
constant tSU : time := 3 ns;
signal data : std_logic := '0';
signal ref : std_logic := '0';

-- This procedure could be in a package with some other similar procedures
procedure SetupCheckProcedure (signal d,r : in std_logic; constant tSU : in time) is
begin
wait until rising_edge(r);
if (d'last_event < tSU or d = 'X' or d = 'U') then
report "SetupCheckProcedure: Setup failure, expected " & time'image(tSU) & ", got " & time'image(d'last_event) & "." severity warning;
end if;
end procedure;
begin
ref <= not ref after tCK / 2;
-- Data toggling out of sync with ref
data <= not data after (tCK - 1 ns);

SetupChecker : entity work.SetupCheckEntity
generic map (
tSU => tSU
)
port map (
data_event => data,
ref_event => ref
);

SetupCheckProcedure(data, ref, tSU);
end;

代替report，你可以使用一些日志包或写入文件。

如果您认为"哇，所有的代码来替换SystemVerilog一行"，请记住，在编写过程之后，您只需要SetupCheckProcedure(data, ref, tSU);，它与问题中的内置函数非常相同。