我的输出总是驱动10110模式检测器的Z值

Question

pattern_det始终驱动z，待检测的模式为10110块FSM如下:

重置,祝辞S1(0)——在S2(1)——在S3(10) -在S4(101)——在S5(1011)——在S1 (0)

在S5，如果我们得到0，那么转变发生在S1,pattern_det得到1。

module patterndetector (clk,rst,data_in,pattern_det);
parameter SRST = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
input clk,rst,data_in;
output reg pattern_det;
reg [2:0]state,nxtstate;
always@(posedge clk) begin
if(rst == 1)begin
pattern_det = 0;
state <= SRST;
nxtstate <= SRST;
end
else begin

case(state)
SRST: begin
if(data_in == 0) begin
nxtstate <= S1;
pattern_det <= 0;
end
else begin
nxtstate <= SRST;
pattern_det <= 0;
end
end
S1:begin
if(data_in == 1) begin
nxtstate <= S2;
pattern_det <= 0;
end
else begin
nxtstate <= S1;
pattern_det <= 0;
end
end
S2:begin
if(data_in ==1) begin
nxtstate <= S2;
pattern_det <= 0;
end
else begin
nxtstate <= S3;
pattern_det <= 0;
end
end
S3:begin
if(data_in == 1) begin
nxtstate <= S4;
pattern_det <= 0;
end
else begin
nxtstate <= S1;
pattern_det <= 0;
end
end
S4:begin
if(data_in == 1) begin
nxtstate <= S5;
pattern_det <= 0;
end
else begin
nxtstate <= S3;
pattern_det <= 0;
end

end
S5:begin
if(data_in == 0) begin
nxtstate <= S1;
pattern_det <= 1;
end
else begin
nxtstate <= S2;
pattern_det <= 0;
end
end
default : pattern_det <= 0;
endcase
end 
end
always@(nxtstate) begin
state <= nxtstate;
end

endmodule

// TEST BENCH
`include "patterndetector.v"
module tb();
reg clk,rst,data_in;
wire pattern_det;
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
repeat(2) @(posedge clk);
rst = 0;
repeat(500) begin
@(posedge clk);
data_in = $random;
end 
#10;
$finish;
end
initial
begin
$monitor("%t: clk = %b, rst = %b, data_in = %b, pattern_det = %b", $time,clk,rst,data_in,pattern_det);
end
endmodule

Answer 1

测试台上的pattern_det线始终是Z，因为它不受任何东西驱动。

您需要在测试台中添加设计模块(patterndetector)的实例。简单地编译两个模块并使用`include是不够的。例如:

module tb();
reg clk,rst,data_in;
wire pattern_det;
patterndetector dut (
.clk          (clk),
.data_in      (data_in),
.rst          (rst),
.pattern_det  (pattern_det)
);
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
// etc.

显示pattern_det为0和1的部分输出:

120: clk = 0, rst = 0, data_in = 1, pattern_det = 0
125: clk = 1, rst = 0, data_in = 0, pattern_det = 1
130: clk = 0, rst = 0, data_in = 0, pattern_det = 1
135: clk = 1, rst = 0, data_in = 1, pattern_det = 0