Verilog数组偏移量

Question

module inst_mem(inst_out, pc_addr_out, clk, rstb);
output reg [31:0] inst_out;
input             clk, rstb;
input      [7:0]  pc_addr_out;
reg        [31:0] array[7:0];
//integer           n = 0;
initial begin 
array[0] <= 32'b00001111000011110000111100001111;
array[1] <= 32'b00011111000011110000111100001111; 
array[2] <= 32'b00101111000011110000111100001111;
array[3] <= 32'b00111111000011110000111100001111;
array[4] <= 32'b01001111000011110000111100001111;
array[5] <= 32'b01011111000011110000111100001111;
array[6] <= 32'b01101111000011110000111100001111;
array[7] <= 32'b01111111000011110000111100001111;
end 
always @(posedge clk or negedge rstb)
if (!rstb)
inst_out <= 32'd0;
else begin
inst_out <= array[pc_addr_out];
//  inst_out <= array[n];
end
endmodule

我为指令存储器编写代码，我发现当我访问像这样的reg类型的数组时，第一个时钟延迟

inst_out <= array[pc_addr_out];

但是当我访问整数类型'n'的数组

inst_out <= array[n];

它工作正常。我想访问一个整数类型的数组但是我不知道怎么做。我试着像C语言一样铸造，但它不起作用。有什么好方法来改变reg类型int类型?

Answer 1

问题在于输入和输出的时间，而不是类型。你的内存是一个ROM，它应该只是组合逻辑，不需要时钟或复位。

module inst_mem(
output wire [31:0] inst_out,
input  wire [7:0]  pc_addr_out
);
reg        [31:0] array[7:0];
initial begin 
array[0] <= 32'b00001111000011110000111100001111;
array[1] <= 32'b00011111000011110000111100001111; 
array[2] <= 32'b00101111000011110000111100001111;
array[3] <= 32'b00111111000011110000111100001111;
array[4] <= 32'b01001111000011110000111100001111;
array[5] <= 32'b01011111000011110000111100001111;
array[6] <= 32'b01101111000011110000111100001111;
array[7] <= 32'b01111111000011110000111100001111;
end 
assign inst_out <= array[pc_addr_out];
end
endmodule