我得到以下端口错误。有人能纠正这个吗?我附加了所有使用端口的代码段。
主要模块`timescale 1ns / 1ps
module northlast_(
input [15:0] a1,a2,a3,a4,
input [1:0] c_x, c_y,
output reg [3:0] port
);
wire [1:0] s_x, s_y,d_x, d_y;
mesh u1(
.a(a1),
.c_x(c_x),
.c_y(c_y),
.port(port),
.s_x(s_x),
.s_y(s_y),
.d_x(d_x),
.d_y(d_y)
);
mesh u2(
.a(a2),
.c_x(c_x),
.c_y(c_y),
.port(port),
.s_x(s_x),
.s_y(s_y),
.d_x(d_x),
.d_y(d_y)
);
mesh u3(
.a(a3),
.c_x(c_x),
.c_y(c_y),
.port(port),
.s_x(s_x),
.s_y(s_y),
.d_x(d_x),
.d_y(d_y)
);
mesh u4(
.a(a4),
.c_x(c_x),
.c_y(c_y),
.port(port),
.s_x(s_x),
.s_y(s_y),
.d_x(d_x),
.d_y(d_y)
);
endmodule
`timescale 1ns / 1ps
module mesh (
input [15:0] a,
input [1:0] c_x,
input [1:0] c_y ,
output reg [3:0] port,
output reg [1:0] s_x,
output reg [1:0] s_y,
output reg [1:0] d_x,
output reg [1:0] d_y
);
reg d_x=0,d_y=0,s_x=0,s_y=0;
always @ (*)//when cx or cy changes, this loop happens
begin
d_y=a[1:0];// x coordinate of destination address
d_x=a[3:2];//y coordinate of destination address
s_y=a[5:4];// x coordinate of source addres
s_x=a[7:6];// y coordinate of source addres
if (d_y>c_y && d_y!= c_y)
port = {c_x,c_y +2'b1};//east
else if (d_y<c_y && d_y!= c_y )
begin
if ( c_y==0)
port = {c_x,c_y +2'b1};//west
else
port = {c_x,c_y -2'b1};//east
end
else if (d_x<c_x && d_y== c_y)
port = {c_x-2'b1,c_y}; //south
else if (d_x>c_x && d_y== c_y )
port = {c_x+2'b1,c_y};//north
end
endmodule
testbench:
`timescale 1ns / 1ps
module northlast_tb;
reg [15:0] a1,a2,a3,a4;
reg [1:0] c_x, c_y;
wire [3:0] port;
northlast_ u1(
.a1(a1),
.a2(a2),
.a3(a3),
.a4(a4),
.c_x(c_x),
.c_y(c_y),
.port(port)
);
initial
begin
a1[15:0] = 16'b0011001101001010;//
c_x=2'b01;
c_y =2'b00;
#5
c_x=2'b01;
c_y =2'b01;
#5
c_x=2'b01;
c_y =2'b10;
#5
/* c_x=2'b11;
c_y =2'b11;
#5*/
a2[15:0] = 16'b0011001110001101;//
c_x=2'b10;
c_y=2'b00;
#5
c_x=2'b10;
c_y =2'b01;
#5
a3[15:0] = 16'b0101001111001010;//
c_x=2'b11;
c_y =2'b00;
#5
c_x=2'b11;
c_y =2'b01;
#5
c_x=2'b11;
c_y =2'b10;
#5
a4[15:0] = 16'b0011001100010111;//
c_x=2'b00;
c_y =2'b01;
#5
c_x=2'b00;
c_y =2'b10;
#5
c_x=2'b00;
c_y =2'b11;
#5
$finish;
end
endmodule
这个错误信息:
ERROR: [VRFC 10-529] concurrent assignment to a non-net port is not permitted [D:/Vivado/northlast/northlast.srcs/sources_1/new/northlast_.v:14]
ERROR: [VRFC 10-529] concurrent assignment to a non-net port is not permitted [D:/Vivado/northlast/northlast.srcs/sources_1/new/northlast_.v:25]
ERROR: [VRFC 10-529] concurrent assignment to a non-net port is not permitted [D:/Vivado/northlast/northlast.srcs/sources_1/new/northlast_.v:36]
ERROR: [VRFC 10-529] concurrent assignment to a non-net port is not permitted [D:/Vivado/northlast/northlast.srcs/sources_1/new/northlast_.v:47]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
不能将reg连接到模块实例的输出端口
在module northlast_声明中将output reg [3:0] port改为output [3:0] port(使其成为错误消息所指的"net")