我的VHDL代码有问题。我收到一个错误
"未解析的信号"temp"有多个来源&"。
我尝试了不同的方法：首先，我有这个：
adc_integer_expected <= integer(volt_db(index)(lane) / (ADC_VOLT_MAX/4096.0));
但它引起了一个错误，告诉我"；期望的adc_整数；有多个来源。所以我决定把它切成两块，像这样：
temp <= (volt_db(index)(lane)) / (ADC_VOLT_MAX/4096.0);
adc_integer_expected <= integer(temp);
但现在我有两个有多个来源的信号："temp"one_answers"adc_integer_expected">
谢谢你的帮助。
这是代码：
library IEEE, modelsim_lib;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
use modelsim_lib.util.all;
library work;
use work.pkg_tool_box.all;
use work.bench_package.all;
use work.func_package.all;
use std.textio.all;
use std.env.all;
architecture sc_0010 of SC_WRAPPER is
--Constants
constant INCR_TH : integer range 0 to 4095:= 1;
signal INCR_VOLT : real := 0.1;
constant ADC_VOLT_MAX : real := 3.0; -- Reference
signal lane_incr : integer := 0;
--signal cnt : integer range 0 to ;
signal spy_thresholds : t_th_x;
signal spy_voltages : t_voltage_in;
signal spy_adc_cntr : t_adc_mes;
signal spy_voltage_adc : t_adc_in;
signal spy_th_comp_rslt : std_logic_vector(11 downto 0);
signal spy_ir_spi : std_logic_vector(15 downto 0);
signal spy_mux_addr : std_logic_vector(2 downto 0);
signal spy_en_mux : std_logic;
--signal spy_adc_miso : std_logic_vector(3 downto 0);
--signal spy_adc_model_out :
signal th_db : t_th_x;
signal cnt_clk : integer := 0;
signal obz : integer := 0;
signal irl : integer := 0;
signal irh : integer := 0;
signal th_comp_rslt : std_logic_vector(11 downto 0) := (others => '0');
--Voltages
signal volt_db : t_voltage_in;
signal voltage_i : real := 0.0;
signal th_i : integer range 0 to 4095 := 0;
signal temp : real := 0.0;
--MUX MODEL
signal volt_mux : t_adc_in := (others => 0.0); -- output coming from the
--signal addr_mux
--SPI
--signal data_to_send : std_logic_vector(15 downto 0);
signal sc_ir_spi : std_logic;
signal bit_cnt : integer range 0 to 16;
signal ir_spi_reg : std_logic_vector(15 downto 0);
signal ir_signal : std_logic_vector(3 downto 0);
--ADC MODEL
--signal adc_model_out : std_logic_vector(11 downto 0);
--signal Dout : std_logic_vector(11 downto 0);
--signal adc_integer_expected : integer;
signal adc_mosi_sample : std_logic_vector(11 downto 0);
--signal mux_addr_sc : std_logic_vector( 2 downto 0);
--signal adc_cntrl_out : std_logic_vector(11 downto 0);
signal adc_integer_expected : integer := 0;
signal adc_value_expected : std_logic_vector(11 downto 0) := (others => '0');
signal cnt_volt : integer := 0;
begin
init_signal_spy("/testbench/inst_DUT/p_thresholds" , "/testbench/inst_scenario/spy_thresholds" , 0,-1);
init_signal_spy("/testbench/channel_voltage" , "/testbench/inst_scenario/spy_voltages" , 0,-1);
init_signal_spy("/testbench/inst_DUT/adc_chX_data" , "/testbench/inst_scenario/spy_adc_cntr" , 0,-1);
--init_signal_spy("/TESTBENCH/g_inst_MUX_MODEL/tb_adc_ainp_chx" , "/testbench/inst_scenario/spy_adc_cntr" , 0,-1);
--init_signal_spy("/testbench/tb_adc_miso_chx" , "/testbench/inst_scenario/spy_voltage_adc" , 0,-1);
init_signal_spy("/testbench/inst_DUT/comp_th_rslt" , "/testbench/inst_scenario/spy_th_comp_rslt", 0,-1);
init_signal_spy("/testbench/tb_adc_ainp_chx" , "/testbench/inst_scenario/spy_voltage_adc", 0,-1);
init_signal_spy("/testbench/inst_DUT/spi_th_reg" , "/testbench/inst_scenario/spy_ir_spi", 0,-1);
--init_signal_spy("/TESTBENCH/g_ins_ADC/tb_adc_miso_chx" , "/testbench/inst_scenario/spy_adc_miso" , 0,-1);
--init_signal_spy("/testbench/inst_DUT/MUX_ADDR" , "/testbench/inst_scenario/spy_mux_addr", 0,-1);
--init_signal_spy("/testbench/inst_DUT/inst_th_comparator/cnt_lane","/testbench/inst_th_comparator/spy_lane" , 0,-1);
----------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------
-- Process : allocation
-- Description : Values allocation to the thresholds and the voltages
----------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------
allocation : process
begin
--HW_RST_N <= '0';
--SW_RST_N <= '0';
--SEL_RSM <= '0';
--PWR_ON <= '0';
--CH_HERE <= (others => '1');
--A_MUX <= (others => '0');
--EN_MUX <= (others => '0');
CH_HERE(0) <= '1';
CH_HERE(1) <= '1'; --'0' after 500 ns, '1' after 3 us, '0' after 8 us;
CH_HERE(2) <= '1'; --'1' after 500 ns, '0' after 4 us, '1' after 9 us;
STST_N <= '1';
obz <= 1000;
irl <= 2000;
irh <= 3000;
th_db <= (others => (others => ( (std_logic_vector(to_unsigned(obz,12))), (std_logic_vector(to_unsigned(irl,12))), (std_logic_vector(to_unsigned(irh,12))) )));
volt_db <= (others => (others => 0.0));
--mux_addr_sc <= "010"; -- MUX = 2 at the beginning
--adc_sample <= '0';
--FORCE_EN <= (others => '0');
xprint(""," ******************************************* ");
xprint(""," SCENARIO 1 : Test ... ");
xprint(""," ******************************************* ");
UVLO_N <= '0';
wait for 100 ns;
UVLO_N <= '1';
wait for 0 ns;
--signal_force("/testbench/inst_DUT/ir_rslt", "0000", 0 ns, freeze, -1 ns, 0);
--for th_i in 0 to 4096/INCR_TH loop
for lane in 0 to 7 loop
for channel in 0 to 3 loop
for threshold in 0 to 2 loop
th_db(channel)(lane)(0) <= std_logic_vector(to_unsigned((1000 + lane_incr), 12));
th_db(channel)(lane)(1) <= std_logic_vector(to_unsigned((2000 + lane_incr), 12));
th_db(channel)(lane)(2) <= std_logic_vector(to_unsigned((3000 + lane_incr), 12));
lane_incr <= lane_incr + 1;
--th_db(channel)(lane)(threshold) <= std_logic_vector(to_unsigned(increment((to_integer(unsigned(th_db(channel)(lane)(threshold)))), 4096,INCR_TH), 12));
wait for 0 ns;
xprint("->", "th_db("&ToS(channel)&")("&ToS(lane)&")("&ToS(threshold)&") vaut : " &ToS(th_db(channel)(lane)(threshold)));
signal_force("/testbench/inst_DUT/p_thresholds("&ToS(channel)&")("&ToS(lane)&")("&ToS(threshold)&")", ToS(th_db(channel)(lane)(threshold)), 0 ns , freeze , -1 ns , 0);
end loop;
end loop;
end loop;
xprint("-->", "th_db finito");
--end loop;
-- Another process ???
for volt_i in 0 to integer(ADC_VOLT_MAX/INCR_VOLT) loop -- 3.0/0.1
for lane in 0 to 7 loop
for channel in 0 to 3 loop
--volt_db(channel)(lane) <= increment(volt_db(channel)(lane),ADC_VOLT_MAX,INCR_VOLT);
if(volt_db(channel)(lane) < ADC_VOLT_MAX - INCR_VOLT) then
volt_db(channel)(lane) <= volt_db(channel)(lane) + INCR_VOLT;
INCR_VOLT <= INCR_VOLT + 0.1;
else
volt_db(channel)(lane) <= volt_db(channel)(lane) + INCR_VOLT - ADC_VOLT_MAX;
end if;
wait for 0 ns;
signal_force("/testbench/channel_voltage("&ToS(channel)&")("&ToS(lane)&")", ToS(volt_db(channel)(lane)), 0 ns , freeze , -1 ns , 0); --TESTBENCH
xprint("->", "volt_db("&ToS(channel)&")("&ToS(lane)&") vaut : " &ToS(volt_db(channel)(lane)));
--xprint("->", "spy_voltage("&ToS(channel)&")("&ToS(lane)&") vaut : " &ToS(spy_voltages(channel)(lane)));
end loop;
end loop;
wait for 0 ns;
--for lane in 0 to 7 loop
-- for channel in 0 to 3 loop
-- if(spy_voltages /= volt_db) then
-- xprint("->", "Data error, the voltages of your ADC are different of what is expected. Try again !");
-- xprint("->", "spy voltage("&ToS(channel)&")("&ToS(lane)&") vaut : " &ToS(spy_voltages(channel)(lane)));
-- xprint("->", "volt_db("&ToS(channel)&")("&ToS(lane)&") vaut : " &ToS(volt_db(channel)(lane)));
-- else
-- xprint("-->", "Voltages spy OK");
-- end if;
-- end loop;
--end loop;
--wait until rising_edge(TICK);
end loop;
--wait for 1 us;
--xprint("->", "STST_N assertion");
--ST_ST_N <= '0';
-- wait until ...
--A_MUX <= "001" after 62.5 ns, "010" after 938 ns, "011" after 1875 ns, "100" after 2813 ns, "101" after 3751 ns, "110" after 4689 ns, "111" after 5627 ns;
--EN_MUX <= "1111";
--wait for 1 us;
--CH_HERE <= (others => '1') after 60 ns;
--wait for 50 ns;
--signal_force("/TESTBENCH/tb_en_mux" , "111111111", 0 ns , freeze , -1 ns , 0);
--wait for 50 * T_Tick;
--signal_release("/TESTBENCH/tb_en_mux",0);
--ok_ko()
wait for 1 ms;
xprint("**"," END OF SIMULATION ** ");
stop(2);
end process allocation;
----------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------
-- Process : test
-- Description : Control and verification
---------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------
-- voltage to adc_model_out
-- adc_model_out to adc_ctrl_out (spy)
-- adc_ctrl_out (spy) to th_comparatot_out (SPI)
g_inst_ADC_CTRL_test : for index in 0 to 3 generate -- The four ADC are in parallel so --> generate
test_verif : process -- ADC_MODEL Sampling
--variable adc_integer_expected : integer := 0;
--variable adc_value_expected : std_logic_vector(11 downto 0) := (others => '0');
--variable mux_addr_sc : std_logic_vector(2 downto 0);
--variable adc_sample : std_logic := '0';
-- Data_sampling new name => expected en integer
-- adc_model_out new name => 12 bit expected from voltage
-- adc_model_miso new name => 12 bit sampled from adc_model
begin
--adc_integer_expected <= 0;
for lane in 0 to 7 loop
wait until(falling_edge(SPI_SS_N));
wait for 62.5 ns; -- wait for one clock pulse
--for channel in 0 to 3 loop
if(EN_MUX = '1') then
volt_mux(index) <= volt_db(index)(to_integer(unsigned(MUX_ADDR)));
else
volt_mux(index) <= 0.0;
end if;
--CheckValue(volt_mux(index), spy_voltage_adc(index), "Comparison result for the output of the mux, for channel : "&CHANNEL_NAME(index));
--end loop;
------------------------------------------- Check if the MUX value changes at the good time ---------------------------------------
--wait for 62.5 ns;
--mux_addr_sc <= std_logic_vector(to_unsigned(integer(mux_addr_sc + 1),3));
--CheckValue(MUX_ADDR, mux_addr_sc, "MUX VALUE IN THE SCENARIO is : "&mux_addr_sc &" and the value in the design is : "&MUX_ADDR);
------------------------------------------- Check the value coming from the ADC MODEL ---------------------------------------------
if (EN_MUX = '1') then
temp <= (volt_db(index)(lane)) / (ADC_VOLT_MAX/4096.0);
adc_integer_expected <= integer(temp);
--adc_integer_expected <= integer(volt_db(index)(lane) / (ADC_VOLT_MAX/4096.0));
wait for 0 ns;
adc_value_expected <= std_logic_vector(to_unsigned(adc_integer_expected, 12));
xprint("--", "ADC DATA channel "&CHANNEL_NAME(index)&" lane "&Tos(lane)&" expected value is : "&ToS(adc_integer_expected)&" (="&ToS(adc_value_expected)&")");
------------------------------------------- Check the value coming from the ADC CONTROLER and compare it with the ADC MODEL's value ----------------
for adc_bit in 0 to 14 loop
wait until(rising_edge(ADC_SCK));
if ((2 <= adc_bit) and (adc_bit < 14) ) then
adc_mosi_sample(adc_bit - 2) <= ADC_MISO_CH(index);
end if;
end loop;
wait for 10 ns;
CheckValue(spy_adc_cntr(index),adc_value_expected, "ADC_MODEL output result for Channel : "&CHANNEL_NAME(index)&".");
CheckValue(spy_adc_cntr(index),adc_mosi_sample,"ADC CTRL output result for channel : "&CHANNEL_NAME(index)&".");
end if;
end loop;
--CheckValue(spy_adc_cntr(index), adc_value_expected, "Comparison result for Channel "&CHANNEL_NAME(index)&" ADC_CONTROLER output");
end process test_verif;
end generate g_inst_ADC_CTRL_test;
spi_process : process
begin
wait until (SPI_SS_N = '1');
wait for 10 ns;
for lane in 0 to 7 loop
for th in 0 to 11 loop
case th is
When 0 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(0)(lane)(0)); -- irl_CHANNEL_A
When 1 => th_comp_rslt(th) <= bool_to_std(adc_value_expected <= th_db(0)(lane)(1)); -- irh_CHANNEL_A
When 2 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(0)(lane)(2)); -- obz_CHANNEL_A
When 3 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(1)(lane)(0)); -- irl_CHANNEL_B
When 4 => th_comp_rslt(th) <= bool_to_std(adc_value_expected <= th_db(1)(lane)(1)); -- irh_CHANNEL_B
When 5 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(1)(lane)(2)); -- obz_CHANNEL_B
When 6 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(2)(lane)(0)); -- irl_CHANNEL_C
When 7 => th_comp_rslt(th) <= bool_to_std(adc_value_expected <= th_db(2)(lane)(1)); -- irh_CHANNEL_C
When 8 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(2)(lane)(2)); -- obz_CHANNEL_C
When 9 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(3)(lane)(0)); -- irl_CHANNEL_D
When 10 => th_comp_rslt(th) <= bool_to_std(adc_value_expected <= th_db(3)(lane)(1)); -- irh_CHANNEL_D
When 11 => th_comp_rslt(th) <= bool_to_std(adc_value_expected >= th_db(3)(lane)(2)); -- obz_CHANNEL_D
xprint("->", "th_comp_rslt("&ToS(th)&") vaut : " &ToS(th_comp_rslt(th)));
--xprint("->", "th_db("&ToS(index)&")("&ToS(lane)&")("&ToS(th)&") vaut : " &ToS(th_db(index)(lane)(th)));
end case;
wait for 0 ns;
--wait until rising_edge(MCLKIN);
ir_signal(0) <= th_comp_rslt(0) and th_comp_rslt(1);
ir_signal(1) <= th_comp_rslt(3) and th_comp_rslt(4);
ir_signal(2) <= th_comp_rslt(6) and th_comp_rslt(7);
ir_signal(3) <= th_comp_rslt(9) and th_comp_rslt(10);
wait for 0 ns;
--CheckValue(spy_th_comp_rslt, th_comp_rslt, "Comparison result for IR_SPI(16 bits) "); --&CHANNEL_NAME(index)&Tos(lane)&" "&TH_NAME(th));
end loop;
ir_spi_reg <= ir_signal(3) & th_comp_rslt(11 downto 9) &
ir_signal(2) & th_comp_rslt( 8 downto 6) &
ir_signal(1) & th_comp_rslt( 5 downto 3) &
ir_signal(0) & th_comp_rslt( 2 downto 0);
CheckValue(spy_ir_spi, ir_spi_reg, "IR result for lane number : " &ToS(lane));
end loop;
wait for 1 ms;
stop(2);
end process spi_process;
--end generate g_inst_ADC_CTRL_test;
--output_latched : process
--begin
--
--end process;
end sc_0010;
Temp是在一个进程内部分配的，该进程本身就是生成的。因此，有4个进程驱动信号温度。这与adc_value_expected相同。您需要从这些进程中删除这些信号，或者使它们像进程中使用generate迭代器作为索引的其他信号一样成为一个数组。