为什么除了由凿子生成的ProgramCounter之外，没有其他模块的verilog代码

Question

我正在写一个凿项目，如下所示：凿项目。当我试图通过生成verilog文件时

object Elaborate extends App {
(new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage.ChiselGeneratorAnnotation(() =>new Top())))
}

和命令：

mill -i __.test.runMain Elaborate -td $(BUILD_DIR)

它生成了一个verilog文件：

module ProgramCounter(
input         clock,
input         reset,
output [63:0] io_nowAdd
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [63:0] cntReg; // @[ProgramCounter.scala 12:23]
wire [63:0] _cntReg_T_2 = cntReg + 64'h4; // @[ProgramCounter.scala 13:65]
assign io_nowAdd = cntReg; // @[ProgramCounter.scala 15:13]
always @(posedge clock) begin
if (reset) begin // @[ProgramCounter.scala 12:23]
cntReg <= 64'h80000000; // @[ProgramCounter.scala 12:23]
end else if (cntReg == 64'h8fffffff) begin // @[ProgramCounter.scala 13:16]
cntReg <= 64'h80000000;
end else begin
cntReg <= _cntReg_T_2;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
cntReg = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Top(
input         clock,
input         reset,
output [63:0] io_pcAddr,
input  [31:0] io_inst
);
wire  PC_clock; // @[Top.scala 14:18]
wire  PC_reset; // @[Top.scala 14:18]
wire [63:0] PC_io_nowAdd; // @[Top.scala 14:18]
ProgramCounter PC ( // @[Top.scala 14:18]
.clock(PC_clock),
.reset(PC_reset),
.io_nowAdd(PC_io_nowAdd)
);
assign io_pcAddr = PC_io_nowAdd; // @[Top.scala 18:13]
assign PC_clock = clock;
assign PC_reset = reset;
endmodule

这与除了CCD_ 1之外的其他模块无关。当我检查verilog所基于的Top.fir文件时，它显示：

circuit Top :
module ProgramCounter :
input clock : Clock
input reset : Reset
output io : { nowAdd : UInt<64>}
reg cntReg : UInt<64>, clock with :
reset => (reset, UInt<64>("h80000000")) @[ProgramCounter.scala 12:23]
node _cntReg_T = eq(cntReg, UInt<32>("h8fffffff")) @[ProgramCounter.scala 13:24]
node _cntReg_T_1 = add(cntReg, UInt<3>("h4")) @[ProgramCounter.scala 13:65]
node _cntReg_T_2 = tail(_cntReg_T_1, 1) @[ProgramCounter.scala 13:65]
node _cntReg_T_3 = mux(_cntReg_T, UInt<32>("h80000000"), _cntReg_T_2) @[ProgramCounter.scala 13:16]
cntReg <= _cntReg_T_3 @[ProgramCounter.scala 13:10]
io.nowAdd <= cntReg @[ProgramCounter.scala 15:13]
module Register :
input clock : Clock
input reset : Reset
output io : { flip src1Idx : UInt<5>, flip src2Idx : UInt<5>, src1Data : UInt<64>, src2Data : UInt<64>, flip writeEnable : UInt<1>, flip regWriteIdx : UInt<5>, flip writeDate : UInt<64>}
wire _registerFile_WIRE : UInt<64>[32] @[Register.scala 25:37]
_registerFile_WIRE[0] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[1] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[2] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[3] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[4] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[5] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[6] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[7] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[8] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[9] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[10] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[11] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[12] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[13] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[14] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[15] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[16] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[17] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[18] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[19] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[20] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[21] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[22] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[23] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[24] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[25] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[26] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[27] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[28] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[29] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[30] <= UInt<64>("h0") @[Register.scala 25:37]
_registerFile_WIRE[31] <= UInt<64>("h0") @[Register.scala 25:37]
reg registerFile : UInt<64>[32], clock with :
reset => (reset, _registerFile_WIRE) @[Register.scala 25:29]
registerFile[0] <= UInt<64>("h0") @[Register.scala 28:19]
io.src1Data <= registerFile[io.src1Idx] @[Register.scala 30:15]
io.src2Data <= registerFile[io.src2Idx] @[Register.scala 31:15]
node _registerFile_T = neq(io.regWriteIdx, UInt<1>("h0")) @[Register.scala 33:72]
node _registerFile_T_1 = and(io.writeEnable, _registerFile_T) @[Register.scala 33:54]
node _registerFile_T_2 = mux(_registerFile_T_1, io.writeDate, registerFile[io.regWriteIdx]) @[Register.scala 33:38]
registerFile[io.regWriteIdx] <= _registerFile_T_2 @[Register.scala 33:32]
module InstructionDecoder :
input clock : Clock
input reset : Reset
output io : { flip inst : UInt<32>, srcRegOne : UInt<5>, srcRegTwo : UInt, distanceReg : UInt<5>}
node _io_srcRegOne_T = bits(io.inst, 19, 15) @[InstuctionDecoder.scala 16:26]
io.srcRegOne <= _io_srcRegOne_T @[InstuctionDecoder.scala 16:16]
node _io_srcRegTwo_T = bits(io.inst, 31, 20) @[InstuctionDecoder.scala 17:26]
io.srcRegTwo <= _io_srcRegTwo_T @[InstuctionDecoder.scala 17:16]
node _io_distanceReg_T = bits(io.inst, 11, 7) @[InstuctionDecoder.scala 18:28]
io.distanceReg <= _io_distanceReg_T @[InstuctionDecoder.scala 18:18]
module Adder :
input clock : Clock
input reset : Reset
output io : { flip dataOne : UInt<64>, flip dateTwo : UInt<64>, flip subOrAdd : UInt<1>, dataOut : UInt<64>}
node _io_dataOut_T = sub(io.dataOne, io.dateTwo) @[Adder.scala 17:45]
node _io_dataOut_T_1 = tail(_io_dataOut_T, 1) @[Adder.scala 17:45]
node _io_dataOut_T_2 = add(io.dataOne, io.dateTwo) @[Adder.scala 17:70]
node _io_dataOut_T_3 = tail(_io_dataOut_T_2, 1) @[Adder.scala 17:70]
node _io_dataOut_T_4 = mux(io.subOrAdd, _io_dataOut_T_1, _io_dataOut_T_3) @[Adder.scala 17:20]
io.dataOut <= _io_dataOut_T_4 @[Adder.scala 17:14]
module Top :
input clock : Clock
input reset : UInt<1>
output io : { pcAddr : UInt<64>, flip inst : UInt<32>}
inst PC of ProgramCounter @[Top.scala 14:18]
PC.clock <= clock
PC.reset <= reset
inst Reg of Register @[Top.scala 15:19]
Reg.clock <= clock
Reg.reset <= reset
inst Decoder of InstructionDecoder @[Top.scala 16:23]
Decoder.clock <= clock
Decoder.reset <= reset
inst adder of Adder @[Top.scala 17:21]
adder.clock <= clock
adder.reset <= reset
io.pcAddr <= PC.io.nowAdd @[Top.scala 18:13]
Decoder.io.inst <= io.inst @[Top.scala 19:19]
Reg.io.regWriteIdx <= Decoder.io.distanceReg @[Top.scala 21:22]
Reg.io.writeEnable <= UInt<1>("h1") @[Top.scala 22:22]
Reg.io.src1Idx <= Decoder.io.srcRegOne @[Top.scala 24:18]
Reg.io.src2Idx <= UInt<1>("h0") @[Top.scala 25:18]
adder.io.dataOne <= Reg.io.src1Data @[Top.scala 27:20]
adder.io.dateTwo <= Decoder.io.srcRegTwo @[Top.scala 28:20]
Reg.io.writeDate <= adder.io.dataOut @[Top.scala 30:20]
adder.io.subOrAdd <= UInt<1>("h0") @[Top.scala 31:21]

另一个项目可以在其内容中看到，那么为什么verilog文件缺少它们呢？

Answer 1

发生这种情况是因为电路的外部可见行为不依赖于任何其他模块。我所说的外部可见行为是指顶层输出(在您的情况下为io_nowAdd(以及任何printf或assert语句(您的电路中没有任何语句(的值。

如果要防止编译器删除这些未使用的信号，可以对任何要保留的信号使用dontTouch函数。