进程中的 VHDL 指令未执行

Question

我的任务是设计一个缓存和缓存控制器。我正在从内存中读取16字节的块并将其写入缓存。仅在块的最后一个字节上，data_array不更新并保持0。我已经成功地将一个意外行为隔离为一条指令奇怪地没有执行。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache is
...
port(
...
m_readdata : in std_logic_vector (7 downto 0);
...
);
end cache;
architecture arch of cache is
...
type Data_Array_Type is array (31 downto 0) of std_logic_vector(127 downto 0);
signal data_array : Data_Array_Type := (others=> (others=>'0'));
...
begin
process(clock, reset)
begin
...
data_array (index) (127 downto 120) <= m_readdata;
report "m_readdata: " & integer'image(to_integer(unsigned(m_readdata)));
report "data_array (index) (127 downto 120): " & integer'image(to_integer(unsigned(data_array (index) (127 downto 120))));
...
end process;
end arch;

输出:

# ** Note: m_readdata: 255
#    Time: 195500 ps  Iteration: 0  Instance: /cache_tb/dut
# ** Note: data_array (index) (127 downto 120): 0
#    Time: 195500 ps  Iteration: 0  Instance: /cache_tb/dut

输出显示将m_readdata赋值给data_array的那行不执行。没有其他地方的数据数组被修改。

Answer 1

这太奇怪了。显然，这是因为VHDL在下次运行之前不会更新进程内的值。这里解释得更清楚https://stackoverflow.com/a/13956532/7923070。