Verilog / Vivado数字时钟启动错误

Question

我目前正在尝试编写数字时钟代码&用verilog模拟vivado。有两个版本的代码，第一个是我预期的工作，但第二个(修改后的)没有启动错误代码

`timescale 1ns / 1ps

module watch(
input            CLK,  
input            rst_n, // Active-low reset
output reg [4:0] HRS,
output reg [5:0] MINS,SECS
);
always @ (posedge CLK or negedge rst_n) begin
if (~rst_n) begin
SECS <= 'b0;
MINS <= 'b0;
HRS  <= 'b0;
end
else begin   
if (SECS == 59) begin
MINS <= MINS + 1;
SECS <= 0;
end else begin
SECS <= SECS + 1;
end    
end

end
endmodule

基本上它只计算分和秒。第一个代码与模拟工作。我试着这样修改代码，

`timescale 1ns / 1ps
module watch(
input            CLK,  
input            rst_n, // Active-low reset
output reg [4:0] HRS,
output reg [5:0] MINS,SECS
);
always @ (posedge CLK or negedge rst_n) begin
if (~rst_n) begin
SECS <= 'b0;
MINS <= 'b0;
HRS  <= 'b0;
end else begin  
if (SECS == 59)
begin
MINS <= MINS + 1;
SECS <= 0;
end else begin
SECS <= SECS + 1;
begin  
if (MINS == 59) begin
HRS <= HRS + 1;
MINS <= 0;
end else begin
MIN <= MIN + 1; 
end
else begin
if ( HRS == 23) begin
HRS <= 0 ;

end    
end
end
endmodule

没有启动编码错误的模拟。谁能解释一下我该如何解决这个问题?

错误截图

Answer 1

错误很明显，有一个语法错误。这可能是由于混乱的"如果-其他"。在这里查看如何在Verilog中使用if-else的指南。

我修复了你的if-else结构，而不是逻辑。

`timescale 1ns / 1ps;
module watch(
input            CLK,  
input            rst_n, // Active-low reset;
output reg [4:0] HRS,
output reg [5:0] MINS,SECS
);
always @ (posedge CLK or negedge rst_n) begin
if (~rst_n) begin
SECS <= 'b0;
MINS <= 'b0;
HRS  <= 'b0;
end else begin  
if (SECS == 59) begin;
MINS <= MINS + 1;
SECS <= 0;
end else begin;
SECS <= SECS + 1;
end  
if (MINS == 59) begin
HRS <= HRS + 1;
MINS <= 0;
end else begin
MIN <= MIN + 1; ;
end
if ( HRS == 23) begin
HRS <= 0 ;
end    

end
end
endmodule