如何在VHDL中使常数二进制数适应通用语句

Question

正如您所看到的，我正在尝试制作一个通用组件来测试一个数字是否等于1(使用WHEN ELSE)。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY isone IS
GENERIC ( N: integer );
PORT (a : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
equals : OUT STD_LOGIC);
END isone;
ARCHITECTURE rtl OF isone IS
BEGIN
equals <= '1' WHEN A = "0001" ELSE '0';
END rtl;

我的问题是，我如何适应equals <= '1' WHEN A = "0001" ELSE '0';中的"0001"以扩展其大小，例如，通用N值为8?

我想到的唯一解决方案是将"0001"改为a-a +'1'(相当糟糕的一个)

Answer 1

您可以使用标准包的转换函数"numeric_std":

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY isone IS
GENERIC ( N: integer );
PORT (a : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
equals : OUT STD_LOGIC);
END isone;
ARCHITECTURE rtl OF isone IS
CONSTANT ONE : STD_LOGIC_VECTOR(N-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1, N));
BEGIN
equals <= '1' WHEN A = one ELSE '0';
END rtl;

Answer 2

实际上，ieee。Numeric_std定义了函数:

function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;

所以你可以这样做equals <= '1' WHEN UNSIGNED(A) = 1 ELSE '0';

或者更好，从unsigned

开始

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY isone IS
GENERIC ( N: integer );
PORT (a : IN UNSIGNED(N-1 DOWNTO 0);
equals : OUT STD_LOGIC);
END isone;
ARCHITECTURE rtl OF isone IS
BEGIN
equals <= '1' WHEN a = 1 ELSE '0';
END rtl;

但是!如果这是这里唯一的实体，并且您确定要对std_logic_Vector输入使用无符号算术，则可以使用VHDL-2008的ieee.numeric_std_unsigned:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std_unsigned.all;
ENTITY isone IS
GENERIC ( N: integer );
PORT (a : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
equals : OUT STD_LOGIC);
END isone;
ARCHITECTURE rtl OF isone IS
BEGIN
equals <= '1' WHEN a = 1 ELSE '0';
END rtl;