位比较器语法错误

Question

我正试图为一位比较器编写代码，但我一直得到错误。任何帮助吗?

//onebit_comparator code
module onebit_comparator(
input wire a,b; 
output wire equation);
wire X0,X1;
assign X0 = -a & b;
assign X1 = a & b;
assign equation = X0|X1;
endmoule;

错误

10170 Verilog HDL syntax error at onebit_comparator.v(4) neat text: "output"; expecting ")".
10112 Ignored design unit "onebit_comparator" at onebit_comaparator.v(2) due to previous errors
10170 Verilog HDL syntax error at onebit_comparator.v(12) near text: ";"; expecting a description 

Answer 1

你有两个语法错误和一个打字错误。

改变:

input wire a,b;

:

input wire a,b,

您必须使用逗号而不是分号来分隔端口。

endmoule为错别字;你想输入endmodule

endmodule关键字(或其他end类型的关键字，如endcase等)后不能使用分号。

下面是没有语法错误的完整代码:

module onebit_comparator( 
input wire a,b,
output wire equation);
wire X0,X1;
assign X0 = -a & b;
assign X1 = a & b;
assign equation = X0|X1;
endmodule