我正在尝试用VHDL-2008实现一个通用的反序列化程序。(具体来说，我的目标是Vivado可以在VHDL-2008模式下合成的东西(。
我在下面包含了我当前的代码。实体端口声明为反序列化的输出字指定一个不受约束的std_logic_vector DATA_OUT。
问题是，在这个实现中，如果我想处理32位字，我需要指定一个CounterType，如下所示：
type CounterType is range 0 to 31;
我还没能找到一种方法，用有效的VHDL从DATA_out端口的大小编写CounterType的定义，更不用说Vivado编译器可以接受的方法了。
有办法做到这一点吗？(即，定义范围类型，其中范围对应于无约束实际参数的范围？(
如果不是，我有什么选择来保持这个反序列化器实现尽可能通用，即能够为不同的输出字大小实例化它？
(注意：我更喜欢一种不向实体接口添加泛型的方式，因为在实例化时，这对于DATA_OUT范围的规范来说似乎是多余的。但如果不能以其他方式完成，我也会对这些类型的解决方案感兴趣。(
library ieee;
use ieee.std_logic_1164.all;
entity deserializer is
-- The deserializer accepts its single input bit DATA_IN whenever (DATA_IN_VALID and DATA_IN_READY) = '1'.
-- The deserializer drops its output word DATA_OUT and proceeds whenever (DATA_OUT_VALID and DATA_OUT_READY) = '1'.
port (
CLK : in std_logic;
RESET : in std_logic;
DATA_IN : in std_logic;
DATA_IN_VALID : in std_logic;
DATA_IN_READY : out std_logic;
DATA_OUT : out std_logic_vector;
DATA_OUT_VALID : out std_logic;
DATA_OUT_READY : in std_logic
);
end entity deserializer;
architecture arch of deserializer is
-- This implementation is designed to have no wait states: if a continuous stream of input bits is offered,
-- and the deserializer can offload its output words unimpeded, DATA_IN_READY will always be true, i.e.,
-- we'll never throttle our input; we'll process 1 bit per clock cycle.
type CounterType is range 0 to 31; -- should correspond to the index range of DATA_OUT.
type StateType is record
-- Internal state.
counter : CounterType;
data_in_bit : std_logic; -- Used to store an input bit while waiting to offload the output word in state (counter == 0).
-- Output registers.
data_in_ready : std_logic;
data_out : std_logic_vector(DATA_OUT'range);
data_out_valid : std_logic;
end record StateType;
constant reset_state : StateType := (
counter => 0,
data_in_bit => '-',
data_in_ready => '1',
data_out => (others => '-'),
data_out_valid => '0'
);
signal current_state : StateType := reset_state;
signal next_state : StateType;
begin
combinatorial: process (all) is
variable state: StateType;
begin
-- Calculate next state based on current state and inputs.
if RESET = '1' then
-- Handle synchronous reset.
state := reset_state;
else
-- Start from current state.
state := current_state;
if state.counter = 0 then
-- Note: we may have a pending output, waiting to be accepted.
if state.data_out_valid = '1' and DATA_OUT_READY = '1' then
state.data_out := (others => '-');
state.data_out_valid := '0';
end if;
if state.data_in_ready = '1' and DATA_IN_VALID = '1' then
state.data_in_bit := DATA_IN;
state.data_in_ready := '0';
end if;
if state.data_out_valid = '0' and state.data_in_ready = '0' then
state.data_out(state.data_out'right) := state.data_in_bit;
state.data_in_bit := '-';
state.counter := state.counter + 1;
state.data_in_ready := '1';
end if;
else
if state.data_in_ready = '1'and DATA_IN_VALID = '1' then
state.data_out := state.data_out sll 1;
state.data_out(state.data_out'right) := DATA_IN;
if state.counter = CounterType'high then
state.data_out_valid := '1';
state.counter := 0;
else
state.counter := state.counter + 1;
end if;
end if;
end if;
end if;
-- Schedule next state for update at next rising clock edge.
next_state <= state;
-- Drive entity outputs from current state.
DATA_IN_READY <= current_state.data_in_ready;
DATA_OUT <= current_state.data_out;
DATA_OUT_VALID <= current_state.data_out_valid;
end process combinatorial;
sequential: process (CLK) is
begin
if rising_edge(CLK) then
current_state <= next_state;
end if;
end process sequential;
end architecture arch;
CounterType的大小可以由DATA_OUT'low to DATA_OUT'high决定。您不应该声明一个完整的新整数类型，该类型与名为ìnteger`的预定义整数类型不兼容，而应该声明一个子类型，如下所示：
subtype CounterType is integer range DATA_OUT'low to DATA_OUT'high;
如果工具完全符合VHDL-2008，它也应该接受以下内容：
subtype CounterType is integer range DATA_OUT'range;