从VHDL代码输入的5位数组长度不正确

Question

我正在尝试创建一个5位输入32位输出空间，但在测试台架部分，我得到一个错误，上面写着:

COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 18 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 17 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 16 14
COMP96 ERROR COMP96_0367: "Improper array length (4). Expected length is 5." "testbench.vhd" 15 26

测试台架代码如下:

library IEEE;
use IEEE.std_logic_1164.all;
entity rom_test is
end entity rom_test;
architecture dataflow of rom_test is
signal input_address: std_logic_vector (4 downto 0);
signal output_data: std_logic_vector (31 downto 0);

begin
g1: entity work.rom(dataflow)
port map(addr=>input_address, data_out=>output_data);

input_address <= x"0",
x"01" after 20 ns,
x"02" after 40 ns,
x"03" after 60 ns;
end architecture dataflow;

有人能帮忙吗?

Answer 1

input_address是一个长度为5(4到0)的std_logic_vector .您正在尝试为其分配一个长度为4和8的一位数或两位十六进制值。

解决这个问题的一种方法是将一个0连接到一个十六进制数字，得到一个长度为5的向量:

input_address <= '0' & x"0",
'0' & x"1" after 20 ns,
'0' & x"2" after 40 ns,
'0' & x"3" after 60 ns;

另一种方法是只分配input_address的最低4位:

input_address(4) <= '0';
input_address(3 downto 0) <= x"0",
x"1" after 20 ns,
x"2" after 40 ns,
x"3" after 60 ns;