是否有将一些代码合成到verilog内置基元中的选项

Question

我以为没有任何参数的techmap会做到，但事实并非如此。我可能误解了"逻辑合成"的意思。

基本示例：

AND_GATE.v:

module AND_GATE( input A, input B, output X);
assign X = A & B;
endmodule

yosys> read_verilog AND_GATE.v
yosys> synth
....................
Number of wires:                  3
Number of wire bits:              3
Number of public wires:           3
Number of public wire bits:       3
Number of memories:               0
Number of memory bits:            0
Number of processes:              0
Number of cells:                  1
$_AND_                          1
yosys> abc -g AND,NAND,OR,NOR,XOR,XNOR
........................
3.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        1
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        1
Removing temp directory.
yosys> clean
Removed 0 unused cells and 3 unused wires.
yosys> write_verilog net.v

net.v

module AND_GATE(A, B, X);
(* src = "AND_GATE.v:1" *)
input A;
(* src = "AND_GATE.v:1" *)
input B;
(* src = "AND_GATE.v:1" *)
output X;
assign X = B & A;
endmodule

Answer 1

使用类似synth; abc -g AND,NAND,OR,NOR,XOR,XNOR的东西会映射到一组与Verilog基元等效的基本门-techmap本身也不会让你远离它-但Yosys Verilog后端没有使用内置基元的选项，它总是将门作为它们的表达式写入。