如何使用System Verilog编写换行计算代码,参数为hsize[2:0] hburst[2:0] &hadr[31:0]在随机约束下
class adddress_cal;
rand bit[31:0]haddr;
rand bit[2:0]hsize;
rand bit[2:0]hburst;
//how to write the random constraint for wrap address
constraint addr_in_4k { haddr%4096 + (hburst + 1 << hsize) <= 4096;}